Unformatted text preview: EL 5473 Introduction to VLSI Design Homework Assignment 2
Due beginning of Class February 9, 2010
1. (Problem 2.1 in text) Consider an nMOS transistor in a 0.6 μm process with W/L= 4/2 λ (i.e., 1.2/0.6 μm). In this process, the gate oxide thickness is 100 Å and the mobility of electrons is 350 cm2/Vs. The threshold voltage is 0.7 V. Plot Ids for Vgs = 0, 1, 2, 3, 4, and 5 V. ANSWER: 0 V I ds Vgs Vt ds 2 2 Vgs Vt 2 Vgs Vt V V V ds ds dsat Vds Vdsat cutoff linear saturation 350 V · . . · F/ · 241.6 Ids,sat = 0uA, 11uA, 204uA, 639uA, 1316uA, and 2234uA for Vgs = 0, 1, 2, 3, 4, and 5 V, respectively.
2500 VGS=5V
2000 IDS (uA) 1500 VDS=VGS‐VT VGS=4V 1000 VGS=3V
500 0 0 1 2 3 4 VGS=2V VGS=1V
5 VDS (V) 2. (Problem 2.2 in text) Show that the current through two transistors in series is equal to the current through a single transistor of twice the length if the transistors are well described by the Shockley model. Specifically show that IDS1 = IDS2 in the figure below when the transistors are in their linear regions: VDS < VDD Vt, VDD > Vt (this is also true in saturation). Hint: Express the currents of the series transistors in terms of V1 and solve for V1. ANSWER: when the transistors working in linear regions, we have · 2· since transistors are working in linear regions. · Now we have (a) (b) (c) · · · · · · · ⁄2. · ⁄2= · . · . Here we assume that By equalizing equation (b) and (c), we can have Then equation (b) becomes · · · 3. (Problem 2.8 in text) Sometimes the substrate is connected to a voltage called the substrate bias to alter the threshold of the transistors. If the threshold of an nMOS transistor is to be raised, should a positive or negative substrate bias be used? ANSWER: See textbook Chapter 2.4.3 Body Effect, we have Hence, to increase threshold voltage, Vsb need to be increased. As a result, without changing source voltage Vs, a negative substrate bias Vb should be provided. 4. (Problem 2.14 in text) Peter Pitfall is offering to license to you his patented noninverting buffer circuit shown below (left). Graphically derive the transfer characteristics for this buffer. Assume βn = βp = β and Vtn = Vtp = Vt. Why is it a bad circuit idea? VDD 2.5 VDD‐VT 2 1.5 Vout 1 0.5 VT
0 0 V0.5 T 1 Vin 1.5 VDD‐2 T V V2.5 DD 5. (Problem 2.15 in text) A novel inverter has the transfer characteristics show in Figure above (right). What are the values of VIL, VIH, VOL, and VOH that give best noise margins? What are these high and low noise margins? ANSWER: VOH = 1.2V VOL = 0.1V VIH = 1.0V VIL = 0.3V NMH = VOH – VIH = 1.2 – 1.0 = 0.2V NML = VIL – VOL = 0.3 – 0.1 = 0.2V 6. (Problem 2.16 in text) Section 2.5.1 graphically determined the transfer characteristics of a static CMOS inverter. Derive analytic expressions for Vout as a function of Vin for regions B and D of the transfer function. Let Vtn = Vtp and βn = βp. ANSWER: Assume Vtn = Vtp = Vt and βn = βp = β Region B: NMOS in saturated region, PMOS in linear region. · · 2· From · · , we have 2· , 2· · 2· · · Region D: NMOS in linear region, PMOS in saturated region. 2· · From 2· , we have · · , 2· · 2· 2· · · ...
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This note was uploaded on 11/02/2010 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.
 Spring '10
 HalenLee
 Gate, Transistor

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