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Unformatted text preview: EL 5473 Introduction to VLSI Design Homework Assignment 4 Due beginning of Class March 27, 2010 1. (Problem 4.10 in text) Consider the two designs of a 2-input AND gate shown below. Give an intuitive argument about which will be faster. Back up your argument with a calculation of the path effort, delay, and input capacitances x and y to achieve this delay. ANSWER: (a) should be faster than (b) because the NAND has the same parasitic delay but lower logical effort than the NOR. In both design, H = 6, B = 1, P = 1 + 2 = 3. For (a), G = (4/3) * 1 = 4/3, F = GBH = 8, f = 8 1/2 = 2.8, D = 2 f + P = 2 * 2.8 + 3 = 8.6 , x = 6C * 1 / f = 2.14C. For (a), G = (5/3) * 1 = 5/3, F = GBH = 10, f = 10 1/2 = 3.2, D = 2 f + P = 2 * 3.2 + 3 = 9.3 , x = 6C * (5/3) / f = 3.16C. 2. (Problem 4.24 in text) An output pad contains a chain of successively larger inverters to drive the (relatively) enormous off-chip capacitance. If the first inverter in the chain has an input capacitance of 20 fF and the off-chip load is 10 pF, how many inverters should be used to drive the load with least...
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This note was uploaded on 11/02/2010 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.
- Spring '10