HW5-Solution

# HW5-Solution - Each input may present a maximum of 30 Î of...

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EL 5473 Introduction to VLSI Design Homework Assignment 5 Due beginning of Class April 6, 2010 1. (Problem 6.18 in text) Sketch pseudo-nMOS 3-input NAND and NOR gates. Label the transistor widths. What are the rising, falling, and average logical efforts of each gate? 2. (Based on problem 6.21 in text, requires Cadence) Use Cadence to simulate a pseudo-nMOS inverter in which the pMOS transistor is half the width of the nMOS transistor. What are the rising, falling, and average logical efforts from hand calculations? What are t pd , t pdf , and t pdr from simulation? Compare. Show your own simulation results here. 3. (Problem 6.28 in text) Sketch a 3-input dual-rail domino OR/NOR gate.

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4. (Problem 6.35 in text) Design a domino circuit to compute F = (A + B)(C + D) as fast as possible.
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Unformatted text preview: Each input may present a maximum of 30 Î» of transistor width. The output must drive a load equivalent to 500 Î» of transistor width. Choose transistor sizes to achieve least delay and estimate this delay in Ï„ . H = 500/30 = 16.7. Consider two-stage design: OR-OR-AND-INVERT + HI-skew INV. G = 2 * 5/6 = 5/3. P = 4 + 5/6 = 29/6. F = GBH = 27.8. f = F 1/2 = 5.27. D = 2 f + P = 15.4 Ï„ . The inverter size is 500 * (5/6) / 5.27 = 79. 5. (Problem 6.40 in text) Sketch 2-input NAND functions using each of the following circuit techniques: a. static CMOS b. pseudo-nMOS c. dual-rail domino d. CPL e. EEPL f. DCVSPG...
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HW5-Solution - Each input may present a maximum of 30 Î of...

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