hdb3_coding

hdb3_coding - Puma 4000 Series Application Note Puma...

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Puma 4000 Series Application Note January 2002 page 1 of 3 Puma Application Note PMA51A1 HDB3 Code Encoding HDB3 is a modified version of the AMI code which produces marks of alternating polarity with a duty cycle of 50% for every bitslot that contains a logic 1 and no marks for the bitslots that contain a logic 0. An example of the AMI coding is shown below. It can be seen that if there is a prolonged steam of logic 0’s without any logic 1’s there will be no marks transmitted and therefore the clock recovery circuit at the receiving end could lose synchronisation with the transmitter clock and therefore bit slips will occur. To overcome this problem the HDB3 coding replaces groups of 4 zeros with either 1 or 2 marks ensuring that there is never more than 3 spaces between the marks and therefore maintaining the clock synchronisation. To enable the decoded to distinguish between normal marks and marks that have been introduced to replace groups of 4 zeros a violation is introduced on the last mark. These violations would produce a DC shift in the signal when it is fed down a long transmission line so the HDB3 encoding inverts the polarity of each violation to ensure that there is no DC build up. The same data stream is shown below with HDB3 encoding. The above example clearly shows how the violations alternate in polarity and the HDB3 coding inserts either 1 or 2 marks depending on the polarity of the last mark and violation. At point A the mark was positive and assuming the last violation was negative, a mark is introduced at point B to cause a “HDB3 violation” indicating the presence of 4 consecutive zeros.
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hdb3_coding - Puma 4000 Series Application Note Puma...

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