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# hw6 - output port receives at most one request then all...

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Zhou, HuanXian (ID: 0225418) HW6 EE136 Instructor: Kang Xi Question 1. In a 16x16 shared memory switch, the speed of each port is 1 Gbps. (a) Suppose the clock rate of the memory r/w is 50 MHz, find the width of the memory data bus. 2NB = bus width * frequency 2*16*1Gbps = bus width x 50 MHz Bus width = 32 Gbps / 50 MHz = 640 bits (b) If the memory has 32-bit of data bus, what is the minimum clock frequency? 2NB = bus width * frequency 2*16*1Gbps = 32 bit x frequency Min. clock frequency = 32 Gbps / 32 bit = 1 Ghz (c) If input-queue architecture is used to build the same switch, and the memory data bus has 32 bits, what is the minimum clock frequency of the memory r/w? 2*1 Gbps = 2Gbps Min. clock frequency = 2 Gbps/32 bit = 62.5 MHz Questions 2. The definition of non-blocking in an NxN switch (N input, N output) is: Consider all the input-output connection requests, if each input port sends out at most one request and each

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Unformatted text preview: output port receives at most one request, then all these connections can be established in the switch. Crossbar switching is non-blocking. Discuss if TSI (time slot interchange) architecture is non-blocking or not. TSI architecture is a non-blocking switch, because we still have an N-to-N output at the output, the only thing that TSI does is to modify the output sequence of the input. Question 3. The following architecture is a combination of TSI and crossbar, where each blue arrow is a TDM link. Discuss if it is possible to use a crossbar architecture plus multiplexers/de-multiplexers to build a switch and avoid the use of TSI? If yes, suppose each TDM link has four time slots (four user channels), draw a figure to show your design. Yes,...
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hw6 - output port receives at most one request then all...

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