timing-notes

timing-notes - ENGIN112: Introduction to Electrical and...

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ENGIN112: Introduction to Electrical and Computer Engineering Fall 2003 Prof. Russell Tessier Understanding Sequential Circuit Timing Perhaps the two most distinguishing characteristics of a computer are its processor clock speed and the size of its main memory. While it is relatively easy to understand the concept of main memory size (the number of storage bits in the computer), the concept of processor clock speed is a little more difficult to grasp. In this document we will explain what is meant by sequential circuit clock speed, and more importantly, how to calculate it using the timing parameters of combinational and sequential circuit components. Clk T per Figure 1: Periodic Clock Signal As we have discussed this term, edge-trigged flip flops, such as the D flip flop, are controlled by a clock signal, such as the signal labeled Clk in Figure 1. A clock signal is a periodic square wave which alternates between logic high (1) and logic low (0) values at predictable times. The amount of time between rising clock edges is called the clock period , T per , of the clock. In modern computers the clock period is usually under 10 nanoseconds (10 ns). The inverse of the clock period ( 1 T per )isthe clock frequency , f . Since the clock is used as the control input to edge- triggered flip flops, the clock frequency measures how often the data is transfered, or clocked , into edge-triggered flip flops. A bigger clock frequency indicates that data is being stored more quickly, and the sequential circuit is generating results at a faster rate. Typical clock frequencies for modern computer systems range from 1 megaHertz (MHz) to around 5 gigaHertz (GHz). 1 Timing Parameters for Combinational Logic When implemented physically, combinational circuits, such as AND and OR gates, exhibit certain timing characteristics. When a binary value (0 or 1) is applied at the input to a combinational circuit, the change at the circuit output is not instantaneous due to electrical constraints. Circuit input-to-output delay in combinational circuits can be expressed with two parameters, t pd and t cd , defined as follows: Propagation delay ( t pd ) - This value indicates the amount of time needed for a change in a logic input to result in a permanent change at an output. Combinational logic is guaranteed not to show any further output changes in response to an input change after t pd time units have passed. 1
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XY t cd t cd tt pd pd X Y Figure 2: Combinational Propagation and Contamination Delay Contamination delay ( t cd ) - This value indicates the amount of time needed for a change in a logic input to result in an initial change at an output [1]. Combinational logic is guaranteed not to show any output change in response to an input change before t cd time units have passed.
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timing-notes - ENGIN112: Introduction to Electrical and...

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