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Pipeline Simulation for Detecting Pipeline Hazards

Pipeline Simulation for Detecting Pipeline Hazards -...

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Assignment 1: Pipeline Simulator / Detecting Pipeline Hazards Due: Tuesday 09/21/10 (before class) In this assignment, you will write a pipeline simulator that reads in a small subset of MIPS instruc- tions, and reports how those instructions would flow through the pipeline. Instructions are read from stdin, and the report is printed to stdout. Sample input/output are given on the final page of this handout. The MIPS instructions you must recognize are a subset of those listed on the inside backcover of your text and chapter 2. They are: loads and stores ( LW , SW , L.S , S.S ) integer operations ( DADD , DSUB , AND , OR , XOR ) FP operations ( ADD.S , SUB.S , MUL.S , DIV.S ) You should first generate a numbered list of instructions. Next, produce a table that indicates for each cycle the number of the instruction that each pipeline stage is processing ( ** if none). Whenever an instruction cannot proceed to the next pipeline stage, that stage should instead print ‘stall’. After the table, you should print associated with the type of hazard the number of stalls, the percentage of total stalls, and the percentage of total cycles caused by that stall class. In addition, you should have a summary line that indicates the total stalls and percentage total cycles that were stalls. You can assume the following distinct pipeline stages: 1. IF : instruction fetch 2. ID : instruction decode 3. HC : Hazard check 4. EX : execute (most integer inst and all load/stores) 5. MEM : memory access 6. WB : integer write back 7. FX1 : stage 1 of fp execute pipeline 8. FX2 : stage 2 of fp execute pipeline 9. FX3 : stage 3 of fp execute pipeline 10. FWB : floating point write back All instructions go through the first three stages, and are stalled if necessary to avoid hazards in HC . In addition to the normal hazards, we will stall in HC to avoid out-of-order completion. More specifically, a following instruction can complete in the same clock cycle as a preceding instruction, but it is never OK for a following instruction to change machine state before the preceding instruction does. After HC , instructions are dispatched to either the beginning of the integer sub-pipe ( EX ), or the beginning of the fp sub-pipe ( FX1 ).
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