243S2008-01 - (4) n+ S/D implant (5) Angle implant (tilted...

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N. CHEUNG, Sp2008 EE243: ADVANCED IC PROCESSING AND LAYOUT Homework Assignment #1 (Due Feb 6, W 9:30am) Reading Assignment EE243 Lecture Notes PGD, Chapter 2 on CMOS process flow Problem 1 Standard CMOS Process flow Read Chapter 2 of PGD and generate a process flow (process step description on left column, sketch of cross section at right right ) of the following CMOS structure. The starting material is p - on p + epi wafer. The well isolation is Shallow trench Isolation (with polyt-Si refill) .The copper metallization has TiN liners. Problem 2 Sub-50nm MOSFET Process Flow Optical lithography typically defines features larger than 50nm. To fabricate MOSFETs with channel length less than 50nm, the following process description is found in a publication: (1) Fabricate oxide trench for device isolation (2) Form silicon nitride on pad-oxide films. (3) Pattern nitride/pad-oxide to smallest feature by optical lithography
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Unformatted text preview: (4) n+ S/D implant (5) Angle implant (tilted ~ 45 degrees ) to form n+ pockets. (6) Form TiSi 2 on S/D regions (7) Deposit CVD oxide and planarize surface by CMP (8) Selectively remove nitride dummy gate (9) Deposit CVD oxide and form oxide spacer by RIE (10) Grow gate oxide by thermal oxidation (11) Poly-Si gate deposition by CVD (12) Pattern Poly-Si gate The final device cross-section is illustrated below. Cu Let us start with a structure with oxide trench isolation already fabricated. Continue the process description with your interpretation of the process flow. Show the cross-sections at major processing steps. Process Description Cross-section 1) Starting structure ( oxide trench isolation) SiO2 SiO2 p-Si SiO2 CVD oxide SiO2 CVD oxide n+ n+ n+ n+ poly-Si gate Thermal gate oxide Oxide spacer Angled Implant n+ pocket Normal S/D implant Smallest feature printable by optical lithography...
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243S2008-01 - (4) n+ S/D implant (5) Angle implant (tilted...

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