243S2008-01-soln - N. CHEUNG, Sp2008 EE243 Homework #1...

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N. CHEUNG, Sp2008 EE243 Homework #1 Solutions Problem 1 Starting Material : p/p+ Trench patterning Reactive ion etching of trench to p+ substrate Strip mask Oxidize trench sidewall Refill with thick CVD poly-Si till planar Etch poly-Si till poly slightly below trench surface Reoxidize poly till trench oxide is planar.[If a really thick oxide is needed to butt against the S/D, an additional oxidation masking step may be necessary] Pattern n-well area n-well implant Pattern p-well area p-well implant Well drive in V T implants for NMOS (mask PMOS) V T implants for PMOS (mask NMOS) Clean surface oxide formed during drive-in Gate oxide oxidation Poly-gate CVD Poly-gate patterning NMOS LDD implant (mask PMOS) PMOS LDD implant (mask NMOS) Reoxidize poly gate Blanket CVD oxide Anisotropic RIE to form gate sidewall spacer NMOS S/D and n+ gate implant (mask PMOS) PMOS S/D and p+ gate implant (mask NMOS) Blanket deposition of Ti Annealing to form silicide on S/D and poly gate Selectively remove unreacted Ti
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This note was uploaded on 11/02/2010 for the course EECS 243 taught by Professor Ee243 during the Spring '03 term at University of California, Berkeley.

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243S2008-01-soln - N. CHEUNG, Sp2008 EE243 Homework #1...

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