CSE502_lec01+2+3-introS10

CSE502_lec01+2+3-introS10 - CSE 502 Graduate Computer...

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Unformatted text preview: CSE 502 Graduate Computer Architecture Lec 1-3 - Introduction Larry Wittie Computer Science, StonyBrook University http://www.cs.sunysb.edu/~cse502 and ~lw Slides adapted from David Patterson, UC-Berkeley cs252-s06 1/25,27 + 2/1/2010 1 CSE502-S10, Lec 01-3 - intro 1/25,27 + 2/1/2010 CSE502-S10, Lec 01-3 - intro 2 Outline • Computer Science at a Crossroads • Computer Architecture v. Instruction Set Arch. • How would you like your CSE502? • What Computer Architecture brings to table – Quantitative Principles of Design – Technology Performance Trends – Careful, Quantitative Comparisons 1/25,27 + 2/1/2010 CSE502-S10, Lec 01-3 - intro 3 • Old Conventional Wisdom: Power is free, Transistors expensive • New Conventional Wisdom: “Power wall” Power expensive, Xtors free (Can put more on chip than can afford to turn on) • Old CW: Can increase Instruction Level Parallelism more via compilers, innovation (Out-of-order, speculation, VLIW, …) • New CW: “ILP wall” law of diminishing returns on more HW for ILP • Old CW: Multiplies are slow, Memory access is fast • New CW: “Memory wall” Memory slow, multiplies fast (200 clock cycles to DRAM memory, 4 clocks for multiply) • Old CW: Uniprocessor performance 2X / 1.5 yrs • New CW: Power Wall + ILP Wall + Memory Wall = Brick Wall – Uniprocessor performance now 2X / 5(?) yrs ⇒ Sea change in chip design: multiple “cores” (2X processors per chip / ~ 2 years) » Increase on-chip number of simple processors that are power efficient » Simple processor “cores” use less power per useful calculation done Crossroads: Conventional Wisdom in Comp. Arch 1/25,27 + 2/1/2010 CSE502-S10, Lec 01-3 - intro 4 1 10 100 1000 10000 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 Performance (vs. VAX-11/780) 25%/year 52%/year ??%/year Crossroads: Uniprocessor Performance • VAX : 25%/year 1978 to 1986 • RISC + x86: 52%/year 1986 to 2002 • RISC + x86: ??%/year 2002 to 2006 From Hennessy and Patterson, Computer Architecture: A Quantitative Approach , 4th edition, October, 2006 1/25,27 + 2/1/2010 CSE502-S10, Lec 01-3 - intro 5 Sea Change in Chip Design • Intel 4004 (1971): 4-bit processor, 2312 transistors, 0.4 MHz, 10 micron PMOS, 11 mm 2 chip • Processor is the new transistor? • RISC II (1983): 32-bit, 5 stage pipeline, 40,760 transistors, 3 MHz, 3 micron NMOS, 60 mm 2 chip (6 x 10 mm) • Today (2006) 125 mm 2 chip, 0.065 micron CMOS = 2312 RISC II+FPU+Icache+Dcache – RISC II shrinks to ~ 0.02 mm 2 at 65 nm – Caches via DRAM or 1 transistor SRAM ( www.t-ram.com ) ? – Proximity Communication via capacitive coupling at > 1 TB/s ? (Ivan Sutherland @ Sun / Berkeley) 1/25,27 + 2/1/2010 CSE502-S10, Lec 01-3 - intro 6 Déjà vu all over again?...
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This note was uploaded on 11/06/2010 for the course CSE 502 taught by Professor Wittie,l during the Spring '08 term at SUNY Stony Brook.

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CSE502_lec01+2+3-introS10 - CSE 502 Graduate Computer...

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