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CSE502_lec06 7-cache - CSE 502 Graduate Computer Architecture Lec 6-7 – Memory Hierarchy Review Larry Wittie Computer Science StonyBrook

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Unformatted text preview: CSE 502 Graduate Computer Architecture Lec 6-7 – Memory Hierarchy Review Larry Wittie Computer Science, StonyBrook University http://www.cs.sunysb.edu/~cse502 and ~lw Slides adapted from David Patterson, UC-Berkeley cs252-s06 2/(snow10)15-17/2010 CSE502-S10, Lec 06+7-cache VM TLB 2 Review from last lecture • Quantify and summarize performance – Ratios, Geometric Mean, Multiplicative Standard Deviation • F&P: Benchmarks age, disks fail,1 point fail danger • Control VIA State Machines and Microprogramming • Just overlap tasks; easy if tasks are independent • Speed Up ≤ Pipeline Depth; if ideal CPI is 1, then: • Hazards limit performance on computers: – Structural: need more HW resources – Data (RAW,WAR,WAW): need forwarding, compiler scheduling – Control: delayed branch, prediction • Exceptions, Interrupts add complexity pipelined d unpipeline Time Cycle Time Cycle CPI stall Pipeline 1 depth Pipeline Speedup × + = 2/(snow10)15-17/2010 CSE502-S10, Lec 06+7-cache VM TLB 3 Outline • Review • Memory hierarchy • Locality • Cache design • Virtual address spaces • Page table layout • TLB design options • Conclusion 2/(snow10)15-17/2010 CSE502-S10, Lec 06+7-cache VM TLB 4 Memory Hierarchy Review 2/(snow10)15-17/2010 CSE502-S10, Lec 06+7-cache VM TLB 5 Since 1980, CPU has outpaced DRAM ... CPU 60% per yr 2X in 1.5 yrs DRAM 9% per yr 2X in 10 yrs 1 DRAM CPU Performance (1/latency) 1 1 Year Gap grew 50% per year Q. How do architects address this gap? A. Put smaller, faster “cache” memories between CPU and DRAM. Create a “memory hierarchy”. 2/(snow10)15-17/2010 CSE502-S10, Lec 06+7-cache VM TLB 6 Apple || (1977) Latencies Steve Wozniak Steve Jobs CPU: 1000 ns DRAM: 400 ns 1977: DRAM faster than microprocessors 2/(snow10)15-17/2010 CSE502-S10, Lec 06+7-cache VM TLB 7 Levels of the Memory Hierarchy CPU Registers 100s Bytes <10s ns Cache K Bytes 10-100 ns 1-0.1 cents/bit Main Memory M Bytes 200ns- 500ns $.0001-.00001 cents /bit Disk G Bytes, 10 ms (10,000,000 ns) 10 - 10 cents/bit -5 -6 Capacity Access Time Cost Tape Almost infinite sec-min 10 cents/bit -8 Registers Cache Memory Disk Tape Instr. Operands Blocks Pages Files Staging Xfer Unit prog./compiler 1-8 bytes cache cntl 8-128 bytes OS 512-4K bytes user/operator Mbytes Upper Level Lower Level faster Larger 2/(snow10)15-17/2010 CSE502-S10, Lec 06+7-cache VM TLB 8 Memory Hierarchy: Apple iMac G5 iMac G5 1.6 GHz 1600 (mem: 7.3) x Apple II 07 Reg L1 Inst L1 Data L2 DRAM Disk Size 1K 64K 32K 512K 256M 80G Latency Cycles, Time 1, 0.6 ns 3, 1.9 ns 3, 1.9 ns 11, 6.9 ns 88, 55 ns 10 7 , 12 ms Let programs address a memory space that scales to the disk size, at a speed that is usually nearly as fast as register access Managed by compiler Managed by hardware Managed by OS, hardware, application Goal: Illusion of large, fast, cheap memory 2/(snow10)15-17/2010 CSE502-S10, Lec 06+7-cache VM TLB 9 iMac’s PowerPC 970 (G5) : All caches on-chip R eg ist er s 1/2 KB 1/2 KB 512K L2 L1 (64K Instruction) L1 (32K Data) 2/(snow10)15-17/2010...
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This note was uploaded on 11/06/2010 for the course CSE 502 taught by Professor Wittie,l during the Spring '08 term at SUNY Stony Brook.

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CSE502_lec06 7-cache - CSE 502 Graduate Computer Architecture Lec 6-7 – Memory Hierarchy Review Larry Wittie Computer Science StonyBrook

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