CSE502_lec10+11-dynamic-schedB_SpeculationS10

CSE502_lec10+11-dynamic-schedB_SpeculationS10 - CSE 502...

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CSE 502 Graduate Computer Architecture Lec 10+11 – More Instruction Level Parallelism Via Speculation Larry Wittie Computer Science, StonyBrook University http://www.cs.sunysb.edu/~cse502 and ~lw Slides adapted from David Patterson, UC-Berkeley cs252-s06
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3/8-10/10 CSE502-S10, Lec 10+11-ILPB 2 Review from Last Time #1 Leverage Implicit Parallelism for Performance: Instruction Level Parallelism Loop unrolling by compiler to increase ILP Branch prediction to increase ILP Dynamic HW exploiting ILP Works when can’t know dependence at compile time Can hide L1 cache misses Code for one machine runs well on another
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3/8-10/10 CSE502-S10, Lec 10+11-ILPB 3 Review from Last Time #2 Reservations stations: renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards Allows loop unrolling in HW Not limited to basic blocks (integer units gets ahead, beyond branches) Helps cache misses as well Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation 360/91 descendants are Pentium 4, Power 5, AMD Athlon/Opteron, …
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3/8-10/10 CSE502-S10, Lec 10+11-ILPB 4 Outline ILP Speculation Speculative Tomasulo Example Memory Aliases Exceptions VLIW Increasing instruction bandwidth Register Renaming vs. Reorder Buffer Value Prediction
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Quiz Advisory Grades (Only Scores Count) 3/8-10/10 CSE502-S10, Lec 10+11-ILPB 5
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3/8-10/10 CSE502-S10, Lec 10+11-ILPB 6 Speculation For Greater ILP Greater ILP: Overcome control dependence by hardware speculating on outcome of branches and executing program as if guesses were correct Speculation fetch, issue, and execute instructions as if branch predictions were always correct Dynamic scheduling only fetches and issues instructions Essentially a data flow execution model : Operations execute as soon as their operands are available
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3/8-10/10 CSE502-S10, Lec 10+11-ILPB 7 Speculation For Greater ILP Three components of HW-based speculation: 1. Dynamic branch prediction to choose which instructions to execute 2. Speculation to allow execution of instructions before control dependences are resolved + Ability to undo effects of incorrectly speculated sequence 3. Dynamic scheduling to deal with scheduling of combinations of basic blocks
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3/8-10/10 CSE502-S10, Lec 10+11-ILPB 8 Adding Speculation to Tomasulo Must separate execution from allowing instruction to finish or “commit” This additional step called instruction commit When an instruction is no longer speculative, allow it to update the register file or memory Requires additional set of buffers to hold results of instructions that have finished execution but have not committed This reorder buffer ( ROB ) is also used to pass results among instructions that may be speculated
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3/8-10/10 CSE502-S10, Lec 10+11-ILPB 9 Reorder Buffer (ROB) In Tomasulo’s algorithm, once an instruction writes its result, any subsequently issued instructions will find
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This note was uploaded on 11/06/2010 for the course CSE 502 taught by Professor Wittie,l during the Spring '08 term at SUNY Stony Brook.

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CSE502_lec10+11-dynamic-schedB_SpeculationS10 - CSE 502...

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