CSE502_lec13+14+15-VectorS10

CSE-V - CSE 502 Graduate Computer Architecture Lec 13-15 – Vector Computers Larry Wittie Computer Science StonyBrook University

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Unformatted text preview: CSE 502 Graduate Computer Architecture Lec 13-15 – Vector Computers Larry Wittie Computer Science, StonyBrook University http://www.cs.sunysb.edu/~cse502 and ~lw Slides adapted from Krste Asanovic of MIT and David Patterson of UCB, UC-Berkeley cs252-s06 3/17-24/10 CSE502-S10, Lec 13+14+15-Vector 2 Outline • Vector Processing Overview • Vector Metrics, Terms • Greater Efficiency than SuperScalar Processors • Examples – CRAY-1 (1976, 1979) 1st vector-register supercomputer – Multimedia extensions to high-performance PC processors – Modern multi-vector-processor supercomputer – NEC ESS • Design Features of Vector Supercomputers • Conclusions • Next Reading Assignment: Chapter 4 MultiProcessors 3/17-24/10 CSE502-S10, Lec 13+14+15-Vector 3 Vector Programming Model + + + + + + [0] [1] [VLR-1] Vector Arithmetic Instructions ADDV v3, v1, v2 v3 v2 v1 v1 Vector Load and Store Instructions LV v1, r1, r2 Base, r1 Stride, r2 Memory Vector Register Scalar Registers r0 r15 Vector Registers v0 v15 [0] [1] [2] [VLRMAX-1] VLR Vector Length Register [63], [127], [255], … 3/17-24/10 CSE502-S10, Lec 13+14+15-Vector 4 Vector Code Example # Scalar Code LI R4, 64 loop: L.D F0, 0(R1) L.D F2, 0(R2) ADD.D F4, F2, F0 S.D F4, 0(R3) DADDIU R1, 8 DADDIU R2, 8 DADDIU R3, 8 DSUBIU R4, 1 BNEZ R4, loop # Vector Code LI VLR, 64 LV V1, R1 LV V2, R2 ADDV.D V3, V1, V2 SV V3, R3 # C code for (i=0; i<64; i++) C[i] = A[i] + B[i]; 3/17-24/10 CSE502-S10, Lec 13+14+15-Vector 5 Vector Arithmetic Execution • Use deep pipeline (=> fast clock) to execute element operations • Simplifies control of deep pipeline because elements in vector are independent (=> no hazards!) V 1 V 2 V 3 V3 <- v1 * v2 Six stage multiply pipeline 3/17-24/10 CSE502-S10, Lec 13+14+15-Vector 6 Vector Instruction Set Advantages • Compact – one short instruction encodes N operations => N*FlOp BandWidth • Expressive, tells hardware that these N operations: – are independent – use the same functional unit – access disjoint registers – access registers in the same pattern as previous instructions – access a contiguous block of memory (unit-stride load/store) OR access memory in a known pattern (strided load/store) • Scalable – can run same object code on more parallel pipelines or lanes 3/17-24/10 CSE502-S10, Lec 13+14+15-Vector 7 Properties of Vector Processors • Each result independent of previous result => long pipeline, compiler ensures no dependencies => high clock rate • Vector instructions access memory with known pattern => highly interleaved memory => amortize memory latency of 64-plus elements => no (data) caches required! (but use instruction cache) • Reduces branches and branch problems in pipelines • Single vector instruction implies lots of work ( ≈ loop) => fewer instruction fetches 3/17-24/10 CSE502-S10, Lec 13+14+15-Vector 8 Spec92fp Operations (Millions) Instructions (M) Program RISC Vector R / V RISC Vector R / V swim256 115 95 1.1x 115 0.8 142x hydro2d...
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This note was uploaded on 11/06/2010 for the course CSE 502 taught by Professor Wittie,l during the Spring '08 term at SUNY Stony Brook.

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CSE-V - CSE 502 Graduate Computer Architecture Lec 13-15 – Vector Computers Larry Wittie Computer Science StonyBrook University

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