CSE502_lec21+22-memoryhier&tuneS10

CSE502_lec21+22-memoryhier&tuneS10 - CSE 502...

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CSE 502 Graduate Computer Architecture Lec 21-22 – Advanced Memory Hierarchy and Application Tuning Larry Wittie Computer Science, StonyBrook University http://www.cs.sunysb.edu/~cse502 and ~lw Slides adapted from David Patterson, UC-Berkeley cs252-s06
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4/28-5/3/10 CSE502-S10 Lec 21+22 Adv. Memory Hieriarchy 2 Outline Eleven Advanced Cache Optimizations Memory Technology and DRAM Optimizations Conclusions
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4/28-5/3/10 CSE502-S10 Lec 21+22 Adv. Memory Hieriarchy 3 Why More on Memory Hierarchy? 1 10 100 1,000 10,000 100,000 1980 1985 1990 1995 2000 2005 2010 Year Performance Memory Processor Processor-Memory Performance Gap Growing
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4/28-5/3/10 CSE502-S10 Lec 21+22 Adv. Memory Hieriarchy 4 Review: 6 Basic Cache Optimizations Reducing hit time 1. Giving Reads Priority over Writes E.g., Read completes before earlier writes in write buffer 2. Avoiding Address Translation during Cache Indexing (limited to caches with small indices) Reducing Miss Penalty 3. Multilevel Caches Reducing Miss Rate 4. Larger Block size (fewer Compulsory misses) 5. Larger Cache size (fewer Capacity misses) 6. Higher Associativity (fewer Conflict misses)
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4/28-5/3/10 CSE502-S10 Lec 21+22 Adv. Memory Hieriarchy 5 Eleven Advanced Cache Optimizations Reducing hit time 1.Small and simple caches 2.Way prediction 3.Trace caches Increasing cache bandwidth 4.Pipelined caches 5.Multibanked caches 6.Nonblocking caches Reducing Miss Penalty 7. Critical word first 8. Merging write buffers Reducing Miss Rate 9. Compiler optimizations Reducing miss penalty or miss rate via parallelism 10.Hardware prefetching 11.Compiler prefetching
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4/28-5/3/10 CSE502-S10 Lec 21+22 Adv. Memory Hieriarchy 6 1. Fast Hit Times via Small, Simple Caches Index tag memory and then compare takes time Small cache can help hit time since smaller memory takes less time to index to find right set of block(s) in cache E.g., fast L1 caches were same smail size for 3 generations of AMD microprocessors: K6, Athlon, and Opteron Also, having a L2 cache small enough to fit on-chip with the processor avoids time penalty of going off chip (~10X longer data latency off-chip) Simple direct mapping Overlap tag check with data transmission since no choice (kill data out if tag bad) Access time estimate for 90 nm using CACTI model 4.0 Median ratios of access time relative to the direct-mapped caches are 1.32, 1.39, and 1.43 for 2-way, 4-way, and 8-way caches - 0.50 1.00 1.50 2.00 2.50 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB Cache size Access time (ns) 1-way 2-way 4-way 8-way
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4/28-5/3/10 CSE502-S10 Lec 21+22 Adv. Memory Hieriarchy 7 2. Fast Hit Times via Way Prediction How to combine fast hit time of Direct Mapped and have the lower conflict misses of 2-way SetAssoc cache? Way prediction : keep extra bits in cache to predict the “way,” or block within the set, of next cache access.
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This note was uploaded on 11/06/2010 for the course CSE 502 taught by Professor Wittie,l during the Spring '08 term at SUNY Stony Brook.

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CSE502_lec21+22-memoryhier&tuneS10 - CSE 502...

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