113D_1_ManualAlgebraic InstructionSet

113D_1_ManualAlgebraic InstructionSet - TMS320C54x DSP...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: TMS320C54x DSP Reference Set Volume 3: Algebraic Instruction Set Literature Number: SPRU179C March 2001 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, license, warranty or endorsement thereof. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for that products or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright © 2001, Texas Instruments Incorporated Preface Read This First About This Manual The TMS320C54x™ DSP is a fixed-point digital signal processor (DSP) in the TMS320™ DSP family and it can use either of two forms of the instruction set: a mnemonic form or an algebraic form. This book is a reference for the algebraic form of the instruction set. It contains information about the instructions used for all types of operations (arithmetic, logical, load and store, conditional, and program control), the nomenclature used in describing the instruction operation, and supplemental information you may need, such as interrupt priorities and locations. For information about the mnemonic form of the instruction set, see TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set, literature number SPRU172. How to Use This Manual The following table summarizes the C54x™ DSP information contained in this book: If you are looking for information about: Arithmetic operations Chapter 2, Instruction Set Summary Conditions for conditional instructions Appendix A, Condition Codes Control register layout Appendix B, CPU Status and Control Registers Example description of instruction Chapter 1, Symbols and Abbreviations Individual instruction descriptions Chapter 4, Assembly Language Instructions Instruction set abbreviations Chapter 1, Symbols and Abbreviations Instruction set classes SPRU179C Turn to: Chapter 3, Instruction Classes and Cycles iii Readto Use This Manual / Notational Conventions How This First If you are looking for information about: Turn to: Instruction set symbols Chapter 1, Symbols and Abbreviations Load and store operations Chapter 2, Instruction Set Summary Logical operations Chapter 2, Instruction Set Summary Program control operations Chapter 2, Instruction Set Summary Status register layout Appendix B, CPU Status and Control Registers Summary of instructions Chapter 2, Instruction Set Summary Notational Conventions This book uses the following conventions. - Program listings and program examples are shown in a special type- face. Here is a segment of a program listing: lms(*AR3+,*AR4+) - In syntax descriptions, the instruction is in a bold typeface and parame- ters are in an italic typeface. Portions of a syntax in bold must be entered as shown; portions of a syntax in italics describe the type of information that you specify. Here is an example of an instruction syntax: lms(Xmem, Ymem) lms is the instruction, and it has two parameters, Xmem and Ymem. When you use lms, the parameters should be actual dual data-memory operand values. A comma and a space (optional) must separate the two values. - The term OR is used in the assembly language instructions to denote a Boolean operation. The term or is used to indicate selection. Here is an example of an instruction with OR and or: lk OR (src) ³ src or [dst] This instruction ORs the value of lk with the contents of src. Then, it stores the result in src or dst, depending on the syntax of the instruction. - Square brackets, [ and ], identify an optional parameter. If you use an optional parameter, specify the information within the brackets; do not type the brackets themselves. iv Read This First SPRU179C Related Documentation From Texas Instruments Related Documentation From Texas Instruments The following books describe the TMS320C54x™ DSP and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477-8924. When ordering, please identify the book by its title and literature number. Many of these documents are located on the internet at http://www.ti.com. TMS320C54x DSP Reference Set, Volume 1: CPU (literature number SPRU131) describes the TMS320C54x™ 16-bit fixed-point general-purpose digital signal processors. Covered are its architecture, internal register structure, data and program addressing, and the instruction pipeline. Also includes development support information, parts lists, and design considerations for using the XDS510™ emulator. TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set (literature number SPRU172) describes the TMS320C54x™ digital signal processor mnemonic instructions individually. Also includes a summary of instruction set classes and cycles. TMS320C54x DSP Reference Set, Volume 3: Algebraic Instruction Set (literature number SPRU179) describes the TMS320C54x™ digital signal processor algebraic instructions individually. Also includes a summary of instruction set classes and cycles. TMS320C54x DSP Reference Set, Volume 4: Applications Guide (literature number SPRU173) describes software and hardware applications for the TMS320C54x™ digital signal processor. Also includes development support information, parts lists, and design considerations for using the XDS510™ emulator. TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) describes the enhanced peripherals available on the TMS320C54x™ digital signal processors. Includes the multichannel buffered serial ports (McBSPs), direct memory access (DMA) controller, interprocessor communications, and the HPI-8 and HPI-16 host port interfaces. TMS320C54x DSP Family Functional Overview (literature number SPRU307) provides a functional overview of the devices included in the TMS320C54x™ DSP generation of digital signal processors. Included are descriptions of the CPU architecture, bus structure, memory structure, on-chip peripherals, and instruction set. SPRU179C Read This First v Related Documentation From Texas Instruments TMS320C54x DSKplus User’s Guide (literature number SPRU191) describes the TMS320C54x™ digital signal processor starter kit (DSK), which allows you to execute custom TMS320C54x DSP code in real time and debug it line by line. Covered are installation procedures, a description of the debugger and the assembler, customized applications, and initialization routines. TMS320C54x Code Composer Studio Tutorial (literature number SPRU327) introduces the Code Composer Studio integrated development environment and software tools for the TMS320C54x. Code Composer User’s Guide (literature number SPRU328) explains how to use the Code Composer development environment to build and debug embedded real-time DSP applications. TMS320C54x Assembly Language Tools User’s Guide (literature number SPRU102) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C54x™ generation of devices. TMS320C54x Optimizing C Compiler User’s Guide (literature number SPRU103) describes the TMS320C54x™ C compiler. This C compiler accepts ANSI standard C source code and produces assembly language source code for the TMS320C54x generation of devices. TMS320C54x Simulator Getting Started (literature number SPRU137) describes how to install the TMS320C54x™ simulator and the C source debugger for the TMS320C54x DSP. The installation for MS-DOS™, PC-DOS™, SunOS™, Solaris™, and HP-UX™ systems is covered. TMS320C54x Evaluation Module Technical Reference (literature number SPRU135) describes the TMS320C54x™ evaluation module, its features, design details and external interfaces. TMS320C54x Code Generation Tools Getting Started Guide (literature number SPRU147) describes how to install the TMS320C54x™ assembly language tools and the C compiler for the TMS320C54x devices. The installation for MS-DOS™, OS/2™, SunOS™, Solaris™, and HP-UX™ 9.0x systems is covered. TMS320C5xx C Source Debugger User’s Guide (literature number SPRU099) tells you how to invoke the TMS320C54x™ emulator, evaluation module, and simulator versions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, command entry, code execution, data management, and breakpoints. It also includes a tutorial that introduces basic debugger functionality. vi Read This First SPRU179C Trademarks Related Documentation From Texas Instruments / Trademarks TMS320C54x Simulator Addendum (literature number SPRU170) tells you how to define and use a memory map to simulate ports for the TMS320C54x™ DSP. This addendum to the TMS320C5xx C Source Debugger User’s Guide discusses standard serial ports, buffered serial ports, and time division multiplexed (TDM) serial ports. Setting Up TMS320 DSP Interrupts in C Application Report (literature number SPRA036) describes methods of setting up interrupts for the TMS320™ DSP family of processors in C programming language. Sample code segments are provided, along with complete examples of how to set up interrupt vectors. TMS320VC5402 and TMS320UC5402 Bootloader (literature number SPRA618) describes the features and operation of the TMS320VC5402 and TMS320UC5402 bootloader. Also discussed is the contents of the on-chip ROM. TMS320C548/C549 Bootloader Technical Reference (literature number SPRU288) describes the process the bootloader uses to transfer user code from an external source to the program memory at power up. (Presently available only on the internet.) TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over 100 third parties that provide various products that serve the TMS320™ DSP family. A myriad of products and applications are offered—software and hardware development tools, speech recognition, image processing, noise cancellation, modems, etc. Trademarks TMS320, TMS320C2x, TMS320C20x, TMS320C24x, TMS320C5x, TMS320C54x, C54x, 320 Hotline On-line, Micro Star, TI, XDS510, and XDS510WS are trademarks of Texas Instruments. HP-UX is a trademark of Hewlett-Packard Company. MS-DOS and Windows are trademarks of Microsoft Corporation. OS/2 and PC-DOS are trademarks of International Business Machines Corporation. PAL® is a registered trademark of Advanced Micro Devices, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SPARC is a trademark of SPARC International, Inc., but licensed exclusively to Sun Microsystems, Inc. SPRU179C Read This First vii Contents Contents 1 Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Lists and defines the symbols and abbreviations used in the instruction set summary and in the individual instruction descriptions. Also provides an example description of an instruction. 1.1 1.2 2 Instruction Set Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Example Description of Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Provides a summary of the instruction set divided into four basic types of operation. Also includes information on repeating a single instruction and a list of nonrepeatable instructions. 2.1 2.2 2.3 2.4 2.5 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Program-Control Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Load and Store Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Repeating a Single Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 3 Instruction Classes and Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the classes and lists the cycles of the instruction set. 4 Assembly Language Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Describes the TMS320C54x DSP assembly language instructions individually. A Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Lists the conditions used in conditional instructions and the combination of conditions that can be tested. B CPU Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Shows the bit fields of the TMS320C54x CPU status and control registers. C Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Defines terms and abbreviations used throughout this book. SPRU179C Contents ix Figures Figures B–1 B–2 B–3 x Processor Mode Status Register (PMST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Status Register 0 (ST0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Status Register 1 (ST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Figures SPRU179C Tables Tables 1–1 1–2 1–3 1–4 2–1 2–2 2–3 2–4 25 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 2–16 2–17 2–18 2–19 2–20 2–21 2–22 2–23 2–24 2–25 2–26 2–27 2–28 A–1 A–2 B–1 Instruction Set Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Opcode Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Instruction Set Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Operators Used in Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Add Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Subtract Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Multiply-Accumulate and Multiply-Subtract Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Double (32-Bit Operand) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Application-Specific Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 AND Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 OR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 XOR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Test Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Call Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Interrupt Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Repeat Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Stack-Manipulating Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Miscellaneous Program-Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Conditional Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Parallel Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Parallel Load and Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Parallel Store and Add/Subtract Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Parallel Store and Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Miscellaneous Load-Type and Store-Type Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Multicycle Instructions That Become Single-Cycle Instructions When Repeated . . . . . . 2-22 Nonrepeatable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Conditions for Conditional Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Groupings of Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Register Field Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 SPRU179C Tables xi Chapter 1 Symbols and Abbreviations This chapter lists and defines the symbols and abbreviations used in the instruction set summary and in the individual instruction descriptions. It also provides an example description of an instruction. Topic Page 1.1 Instruction Set Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Example Description of Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1-1 Instruction Set Symbols and Abbreviations 1.1 Instruction Set Symbols and Abbreviations Table 1–1 through Table 1–4 list the symbols and abbreviations used in the instruction set summary (Chapter 2) and in the individual instruction descriptions (Chapter 4). Table 1–1. Instruction Set Symbols and Abbreviations Symbol Meaning A Accumulator A ALU Arithmetic logic unit AR Auxiliary register, general usage ARx Designates a specific auxiliary register (0 v x v 7) ARP Auxiliary register pointer field in ST0; this 3-bit field points to the current auxiliary register (AR). ASM 5-bit accumulator shift mode field in ST1 (–16 v ASM v 15) B Accumulator B BRAF Block-repeat active flag in ST1 BRC Block-repeat counter bit_code 4-bit value that determines which bit of a designated data memory value is tested by the test bit instruction (0 v bit_code v 15) C16 Dual 16-bit/double-precision arithmetic mode bit in ST1 C Carry bit in ST0 CC 2-bit condition code (0 v CC v 3) CMPT Compatibility mode bit in ST1 CPL Compiler mode bit in ST1 cond An operand representing a condition used by instructions that execute conditionally [d] Delay option DAB D address bus DAR DAB address register dmad 16-bit immediate data-memory address (0 v dmad v 65 535) Dmem Data-memory operand DP 9-bit data-memory page pointer field in ST0 (0 v DP v 511) 1-2 Symbols and Abbreviations SPRU179C Instruction Set Symbols and Abbreviations Table 1–1. Instruction Set Symbols and Abbreviations (Continued) Symbol Meaning dst Destination accumulator (A or B) dst_ Opposite destination accumulator: If dst = A, then dst_ = B If dst = B, then dst_ = A EAB E address bus EAR EAB address register extpmad 23-bit immediate program-memory address FRCT Fractional mode bit in ST1 hi(A) High part of accumulator A (bits 31–16) HM Hold mode bit in ST1 IFR Interrupt flag register INTM Interrupt mode bit in ST1 K Short-immediate value of less than 9 bits k3 3-bit immediate value (0 v k3 v 7) k5 5-bit immediate value (–16 v k5 v 15) k9 9-bit immediate value (0 v k9 v 511) lk 16-bit long-immediate value Lmem 32-bit single data-memory operand using long-word addressing mmr, MMR Memory-mapped register MMRx, MMRy Memory-mapped register, AR0–AR7 or SP n Number of words following the execute conditionally instruction; n = 1 or 2 N Designates the status register modified in the reset or set status register bit, and execute conditionally instructions: N=0 Status register ST0 N=1 Status register ST1 OVA Overflow flag for accumulator A in ST0 OVB Overflow flag for accumulator B in ST0 SPRU179C Symbols and Abbreviations 1-3 Instruction Set Symbols and Abbreviations Table 1–1. Instruction Set Symbols and Abbreviations (Continued) Symbol Meaning OVdst Overflow flag for the destination accumulator (A or B) OVdst_ Overflow flag for the opposite destination accumulator (A or B) OVsrc Overflow flag for the source accumulator (A or B) OVM Overflow mode bit in ST1 PA 16-bit port immediate address (0 v PA v 65 535) PAR Program address register PC Program counter pmad 16-bit immediate program-memory address (0 v pmad v 65 535) Pmem Program-memory operand PMST Processor mode status register prog Program-memory operand [R] Rounding option RC Repeat counter REA Block-repeat end address register rnd Round RSA Block-repeat start address register RTN Fast-return register used in [d]return_fast instruction SBIT 4-bit value that designates the status register bit number modified in the reset or set status register bit, and execute conditionally instructions (0 v SBIT v 15) SHFT 4-bit shift value (0 v SHFT v 15) SHIFT 5-bit shift value (–16 v SHIFT v 15) Sind Single data-memory operand using indirect addressing Smem 16-bit single data-memory operand SP Stack pointer src Source accumulator (A or B) ST0, ST1 Status register 0, status register 1 SXM Sign-extension mode bit in ST1 1-4 Symbols and Abbreviations SPRU179C Instruction Set Symbols and Abbreviations Table 1–1. Instruction Set Symbols and Abbreviations (Continued) Symbol Meaning T Temporary register TC Test/control flag in ST0 TOS Top of stack TRN Transition register TS Shift value specified by bits 5–0 of T (–16 v TS v 31) uns Unsigned XF External flag status bit in ST1 XPC Program counter extension register Xmem 16-bit dual data-memory operand used in dual-operand instructions and some single-operand instructions Ymem 16-bit dual data-memory operand used in dual-operand instructions – – SP Stack pointer value is decremented by 1 + + SP Stack pointer value is incremented by 1 + + PC Program counter value is incremented by 1 Table 1–2. Opcode Symbols and Abbreviations Symbol Meaning A Data-memory address bit ARX 3-bit value that designates the auxiliary register BITC 4-bit bit code CC 2-bit condition code CCCC CCCC 8-bit condition code COND 4-bit condition code D Destination (dst) accumulator bit D=0 D=1 SPRU179C Accumulator A Accumulator B Symbols and Abbreviations 1-5 Instruction Set Symbols and Abbreviations Table 1–2. Opcode Symbols and Abbreviation (Continued) Symbol Meaning I Addressing mode bit I=0 Direct addressing mode I=1 Indirect addressing mode K Short-immediate value of less than 9 bits MMRX 4-bit value that designates one of nine memory-mapped registers (0 v MMRX v 8) MMRY 4-bit value that designates one of nine memory-mapped registers (0 v MMRY v 8) N Single bit NN 2-bit value that determines the type of interrupt R Rounding (rnd) option bit R=0 R=1 S Execute instruction without rounding Round the result Source (src) accumulator bit S=0 Accumulator A S=1 Accumulator B SBIT 4-bit status register bit number SHFT 4-bit shift value (0 v SHFT v 15) SHIFT 5-bit shift value (–16 v SHIFT v 15) X Data-memory bit Y Data-memory bit Z Delay instruction bit Z=0 Z=1 1-6 Execute instruction without delay Execute instruction with delay Symbols and Abbreviations SPRU179C Instruction Set Symbols and Abbreviations Table 1–3. Instruction Set Notations Symbol Meaning Boldface Characters Boldface characters in an instruction syntax must be typed as shown. Example: For the syntax abdst (Xmem, Ymem), you can use a variety of values for Xmem and Ymem, but the word abdst must be typed as shown. italic symbols Italic symbols in an instruction syntax represent variables. Example: For the syntax abdst (Xmem, Ymem), you can use a variety of values for Xmem and Ymem. [x] Operands in square brackets are optional. Example: For the syntax dst = src + Smem [ << SHIFT ], you must use a value for Smem and src; however, SHIFT is optional. # Prefix of constants used in immediate addressing. For short- or long-immediate operands, # is used in instructions where there is ambiguity with other addressing modes that use immediate operands. For example: repeat #15 uses short immediate addressing. It causes the next instruction to be repeated 16 times. repeat 15 uses direct addressing. The number of times the next instruction repeats is determined by a value stored in memory. For instructions using immediate operands for which there is no ambiguity, # is accepted by the assembler. For example, RPTZ A, #15 and RPTZ A, 15 are equivalent. (abc) The content of a register or location abc. Example: (src) means the content of the source accumulator. x→y Value x is assigned to register or location y. Example: (Smem) → dst means the content of the data-memory value is loaded into the destination accumulator. r(n–m) Bits n through m of register or location r. Example: src(15–0) means bits 15 through 0 of the source accumulator. << nn Shift of nn bits left (negative or positive) || Parallel instruction \\ Rotate left // Rotate right x Logical inversion (1s complement) of x |x| Absolute value of x AAh Indicates that AA represents a hexadecimal number SPRU179C Symbols and Abbreviations 1-7 Instruction Set Symbols and Abbreviations Table 1–4. Operators Used in Instruction Set Symbols Operators Evaluation + – ~ Unary plus, minus, 1s complement Right to left * / % Multiplication, division, modulo Left to right + – Addition, subtraction Left to right Left shift, right shift Left to right Logical left shift Left to right << >> <<< < v Less than, LT or equal Left to right > w Greater than, GT or equal Left to right Not equal to Left to right & Bitwise AND Left to right ^ Bitwise exclusive OR Left to right | Bitwise OR Left to right 0 Note: 1-8 != Unary +, –, and * have higher precedence than the binary forms. Symbols and Abbreviations SPRU179C Example Description of Instruction 1.2 Example Description of Instruction This example of a typical instruction description is provided to familiarize you with the format of the instruction descriptions and to explain what is described under each heading. Each instruction description in Chapter 4 presents the following information: - Assembler syntax Operands Opcode Execution Status Bits Description Words Cycles Classes Examples Each instruction description begins with an assembly syntax expression. Labels may be placed either before the instruction on the same line or on the preceding line in the first column. An optional comment field may conclude the syntax expression. Spaces are required between the fields: - Label - Command and operands - Comment SPRU179C Symbols and Abbreviations 1-9 Example Description of Instruction Syntax 1: 2: 3: 4: src = src + Smem src += Smem src = src + Smem << TS src += Smem << TS dst = src + Smem << 16 dst += Smem << 16 dst = src + Smem [ << SHIFT ] dst += Smem [ << SHIFT ] Each instruction description begins with an assembly syntax expression. See Section 1.1 on page 1-2 for definitions of symbols in the syntax. Operands Smem: src, dst: Single data-memory operand A (accumulator A) B (accumulator B) –16 v SHIFT v 15 Operands may be constants or assembly-time expressions that refer to memory, I/O ports, register addresses, pointers, and a variety of other constants. This section also gives the range of acceptable values for the operand types. Opcode 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x The opcode breaks down the various bit fields that make up each instruction. See Section 1.1 on page 1-2 for definitions of symbols in the instruction opcode. Execution 1: 2: 3: 4: (Smem) + (src) ³ src (Smem) << (TS) + (src) ³ src (Smem) << 16 + (src) ³ dst (Smem) [ << SHIFT ] + (src) ³ dst The execution section describes the processing that takes place when the instruction is executed. The example executions are numbered to correspond to the numbered syntaxes. See Section 1.1 on page 1-2 for definitions of symbols in the execution. Status Bits An instruction’s execution may be affected by the state of the fields in the status registers; also it may affect the state of the status register fields. Both the effects on and the effects of the status register fields are listed in this section. Description This section describes the instruction execution and its effect on the rest of the processor or on memory contents. Any constraints on the operands imposed by the processor or the assembler are discussed. The description parallels and supplements the information given symbolically in the execution section. 1-10 Symbols and Abbreviations SPRU179C Example Description of Instruction Words This field specifies the number of memory words required to store the instruction and its extension words. For instructions operating in single-addressing mode, the number of words given is for all modifiers except for long-offset modifiers, which require one additional word. Cycles This field specifies the number of cycles required for a given C54x DSP instruction to execute as a single instruction with data accesses in DARAM and program accesses from ROM. Additional details on the number of cycles required for other memory configurations and repeat modes are given in Chapter 3, Instruction Classes and Cycles. Classes This field specifies the instruction class for each syntax of the instruction. See Chapter 3, Instruction Classes and Cycles, for a description of each class. Example Example code is included for each instruction. The effect of the code on memory and/or registers is summarized when appropriate. SPRU179C Symbols and Abbreviations 1-11 Chapter 2 Instruction Set Summary The TMS320C54x™ DSP instruction set can be divided into four basic types of operations: - Arithmetic operations Logical operations Program-control operations Load and store operations In this chapter, each of the types of operations is divided into smaller groups of instructions with similar functions. With each instruction listing, you will find the best possible numbers for word count and cycle time, and the instruction class. You will also find a page number that directs you to the appropriate place in the instruction set of Chapter 4. Also included is information on repeating a single instruction and a list of nonrepeatable instructions. Topic Page 2.1 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3 Program-Control Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.4 Load and Store Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5 Repeating a Single Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2-1 Arithmetic Operations 2.1 Arithmetic Operations This section summarizes the arithmetic operation instructions. Table 2–1 through Table 2–6 list the instructions within the following functional groups: - Add instructions (Table 2–1) Subtract instructions (Table 2–2 on page 2-3) Multiply instructions (Table 2–3 on page 2-4) Multiply-accumulate instructions (Table 2–4 on page 2-5) Multiply-subtract instructions (Table 2–4 on page 2-5) Double (32-bit operand) instructions (Table 2–5 on page 2-7) Application-specific instructions (Table 2–6 on page 2-8) Table 2–1. Add Instructions W† Cycles† Class Page src = src + Smem 1 1 3A, 3B 4-4 src = src + Smem << TS src + = Smem << TS src = src + Smem << TS 1 1 3A, 3B 4-4 dst = src + Smem << 16 dst + = Smem << 16 dst = src + Smem << 16 1 1 3A, 3B 4-4 dst = src + Smem [ << SHIFT ] dst + = Smem [ << SHIFT ] dst = src + Smem << SHIFT 2 2 4A, 4B 4-4 src = src + Xmem << SHFT src + = Xmem << SHFT src = src + Xmem << SHFT 1 1 3A 4-4 dst = Xmem << 16 + Ymem << 16 dst = Xmem << 16 + Ymem << 16 1 1 7 4-4 dst = src + #lk [ << SHFT ] dst + = #lk [ << SHFT ] dst = src + #lk << SHFT 2 2 2 4-4 dst = src + #lk << 16 dst + = #lk << 16 dst = src + #lk << 16 2 2 2 4-4 dst = dst + src [ << SHIFT ] dst + = src [ << SHIFT ] dst = dst + src << SHIFT 1 1 1 4-4 dst = dst + src << ASM dst + = src << ASM dst = dst + src << ASM 1 1 1 4-4 src = src + Smem + CARRY src + = Smem + CARRY src = src + Smem + C 1 1 3A, 3B 4-8 Syntax Expression src = src + Smem src + = Smem † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 2-2 Instruction Set Summary SPRU179C Arithmetic Operations Table 2–1. Add Instructions (Continued) W† Cycles† Class Page Smem = Smem + #lk 2 2 18A, 18B 4-9 src = src + uns(Smem) 1 1 3A, 3B 4-10 Syntax Expression Smem = Smem + #lk Smem + = #lk src = src + uns(Smem) src + = uns(Smem) † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Table 2–2. Subtract Instructions W† Cycles† Class Page src = src – Smem 1 1 3A, 3B 4-191 src = src – Smem << TS src – = Smem << TS src = src – Smem << TS 1 1 3A, 3B 4-191 dst = src – Smem << 16 dst – = Smem << 16 dst = src – Smem << 16 1 1 3A, 3B 4-191 dst = src – Smem [ << SHIFT ] dst – = Smem [ << SHIFT ] dst = src – Smem << SHIFT 2 2 4A, 4B 4-191 src = src – Xmem << SHFT src – = Xmem << SHFT src = src – Xmem << SHFT 1 1 3A 4-191 dst = Xmem << 16 – Ymem << 16 dst = Xmem << 16 – Ymem << 16 1 1 7 4-191 dst = src – #lk [ << SHFT ] dst – = #lk [ << SHFT ] dst = src – #lk << SHFT 2 2 2 4-191 dst = src – #lk << 16 dst – = #lk << 16 dst = src – #lk << 16 2 2 2 4-191 dst = dst – src << SHIFT dst – = src << SHIFT dst = dst – src << SHIFT 1 1 1 4-191 dst = dst – src << ASM dst – = src << ASM dst = dst – src << ASM 1 1 1 4-191 src = src – Smem – BORROW src – = Smem – BORROW src = src – Smem – C 1 1 3A, 3B 4-195 Syntax Expression src = src – Smem src – = Smem † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. SPRU179C Instruction Set Summary 2-3 Arithmetic Operations Table 2–2. Subtract Instructions (Continued) W† Cycles† Class Page If (src – Smem << 15) w 0 src = (src – Smem << 15) << 1 + 1 Else src = src << 1 1 1 3A, 3B 4-196 src = src – uns(Smem) 1 1 3A, 3B 4-198 Syntax Expression subc(Smem, src) src = src – uns(Smem) src – = uns(Smem) † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Table 2–3. Multiply Instructions W† Cycles† Class Page dst = T * Smem 1 1 3A, 3B 4-103 dst = rnd(T * Smem) dst = rnd(T * Smem) 1 1 3A, 3B 4-103 dst = Xmem * Ymem [, T = Xmem] dst = Xmem * Ymem, T = Xmem 1 1 7 4-103 dst = Smem * #lk [, T = Smem] dst = Smem * #lk , T = Smem 2 2 6A, 6B 4-103 dst = T * #lk dst = T * #lk 2 2 2 4-103 dst = T * hi(A) dst = T * A(32–16) 1 1 1 4-106 B = Smem * hi(A) [, T = Smem] B = Smem * A(32–16), T = Smem 1 1 3A, 3B 4-106 dst = T * uns(Smem) dst = uns(T) * uns(Smem) 1 1 3A, 3B 4-108 dst = Smem * Smem [, T = Smem] dst = square(Smem) [, T = Smem] dst = Smem * Smem, T = Smem 1 1 3A, 3B 4-163 dst = hi(A) * hi(A) dst = square(hi(A)) dst = A(32–16) * A(32–16) 1 1 1 4-163 Syntax Expression dst = T * Smem † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 2-4 Instruction Set Summary SPRU179C Arithmetic Operations Table 2–4. Multiply-Accumulate and Multiply-Subtract Instructions W† Cycles† Class Page src = src + T * Smem 1 1 3A, 3B 4-83 dst = src + Xmem * Ymem [, T = Xmem] dst + = Xmem * Ymem [, T = Xmem] dst = src + Xmem * Ymem, T = Xmem 1 1 7 4-83 dst = src + T * #lk dst + = T * #lk dst = src + T * #lk 2 2 2 4-83 dst = src + Smem * #lk [, T = Smem] dst + = Smem * #lk [, T = Smem] dst = src + Smem * #lk, T = Smem 2 2 6A, 6B 4-83 src = rnd(src + T * Smem) src = rnd(src + T * Smem) 1 1 3A, 3B 4-83 dst = rnd(src + Xmem * Ymem) [, T = Xmem] dst = rnd(src + Xmem * Ymem), T = Xmem 1 1 7 4-83 B = B + Smem * hi(A) [, T = Smem] B + = Smem * hi(A) [, T = Smem] B = B + Smem * A(32–16), T = Smem 1 1 3A, 3B 4-87 dst = src + T * hi(A) dst + = T * hi(A) dst = src + T * A(32–16) 1 1 1 4-87 B = rnd(B + Smem * hi(A) ) [, T = Smem] B = rnd(B + Smem * A(32–16)), T = Smem 1 1 3A, 3B 4-87 dst = rnd(src + T * hi(A) ) dst = rnd(src + T * A(32–16)) 1 1 1 4-87 macd(Smem, pmad, src) src = src + Smem * pmad, T = Smem, (Smem + 1) = Smem 2 3 23A, 23B 4-89 macp(Smem, pmad, src) src = src + Smem * pmad, T = Smem 2 3 22A, 22B 4-91 src = src + uns(Xmem) * Ymem [, T = Xmem] src + = uns(Xmem) * Ymem [, T = Xmem] src = src + uns(Xmem) * Ymem, T = Xmem 1 1 7 4-93 Syntax Expression src = src + T * Smem src += T * Smem † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. SPRU179C Instruction Set Summary 2-5 Arithmetic Operations Table 2–4. Multiply-Accumulate and Multiply-Subtract Instructions (Continued) W† Cycles† Class Page src = src – T * Smem 1 1 3A, 3B 4-96 src = rnd(src – T * Smem) src = rnd(src – T * Smem) 1 1 3A, 3B 4-96 dst = src – Xmem * Ymem [, T = Xmem] dst – = Xmem * Ymem [, T = Xmem] dst = src – Xmem * Ymem, T = Xmem 1 1 7 4-96 dst = rnd(src – Xmem * Ymem) [, T = Xmem] dst = rnd(src – Xmem * Ymem), T = Xmem 1 1 7 4-96 B = B – Smem * hi(A) [, T = Smem] B – = Smem * hi(A) [, T = Smem] B = B – Smem * A(32–16), T = Smem 1 1 3A, 3B 4-99 dst = src – T * hi(A) dst – = T * hi(A) dst = src – T * A(32–16) 1 1 1 4-99 dst = rnd(src – T * hi(A) ) dst = rnd(src – T * A(32–16)) 1 1 1 4-99 src = src + square(Smem) [, T = Smem] src + = square(Smem) [, T = Smem] src = src + Smem * Smem [, T = Smem] src + = Smem * Smem [, T = Smem] src = src + Smem * Smem, T = Smem 1 1 3A, 3B 4-165 src = src – square(Smem) [, T = Smem] src – = square(Smem) [, T = Smem] src = src – Smem * Smem [, T = Smem] src – = Smem * Smem [, T = Smem] src = src – Smem * Smem, T = Smem 1 1 3A, 3B 4-167 Syntax Expression src = src – T * Smem src – = T * Smem † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 2-6 Instruction Set Summary SPRU179C Arithmetic Operations Table 2–5. Double (32-Bit Operand) Instructions W† Cycles† Class Page If C16 = 0 dst = Lmem + src If C16 = 1 dst(39–16) = Lmem(31–16) + src(31–16) dst(15–0) = Lmem(15–0) + src(15–0) 1 1 9A, 9B 4-37 dst = dadst(Lmem, T) If C16 = 0 dst = Lmem + (T << 16 + T) If C16 = 1 dst(39–16) = Lmem(31–16) + T dst(15–0) = Lmem(15–0) – T 1 1 9A, 9B 4-39 src = dbl(Lmem) – src src = dual(Lmem) – src If C16 = 0 src = Lmem – src If C16 = 1 src(39–16) = Lmem(31–16) – src(31–16) src(15–0) = Lmem(15–0) – src(15–0) 1 1 9A, 9B 4-44 dst = dsadt(Lmem, T) If C16 = 0 dst = Lmem – (T << 16 + T) If C16 = 1 dst(39–16) = Lmem(31–16) – T dst(15–0) = Lmem(15–0) + T 1 1 9A, 9B 4-46 src = src – dbl(Lmem) src – = dbl(Lmem) src = src – dual(Lmem) src – = dual(Lmem) If C16 = 0 src = src – Lmem If C16 = 1 src (39–16) = src(31–16) – Lmem(31–16) src (15–0) = src(15–0) – Lmem(15–0) 1 1 9A, 9B 4-49 dst = dbl(Lmem) – T dst = dual(Lmem) – T If C16 = 0 dst = Lmem – (T << 16 + T) If C16 = 1 dst(39–16) = Lmem(31–16) – T dst(15–0) = Lmem(15–0) – T 1 1 9A, 9B 4-51 Syntax Expression dst = src + dbl(Lmem) dst + = dbl(Lmem) dst = src + dual(Lmem) dst + = dual(Lmem) † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem. SPRU179C Instruction Set Summary 2-7 Arithmetic Operations Table 2–6. Application-Specific Instructions W† Cycles† Class Page B = B + |A(32–16)| A = (Xmem – Ymem) << 16 1 1 7 4-2 dst = |src| dst = |src| 1 1 1 4-3 dst = ~src dst = ~src 1 1 1 4-32 delay(Smem) (Smem + 1) = Smem 1 1 24A, 24B 4-41 T = exp(src) T = number of sign bits (src) – 8 1 1 1 4-53 firs(Xmem, Ymem, pmad) B = B + A * pmad A = (Xmem + Ymem) << 16 2 3 8 4-60 lms(Xmem, Ymem) B = B + Xmem * Ymem A = A + Xmem << 16 + 215 1 1 7 4-81 dst = max(A, B) dst = max(A, B) 1 1 1 4-101 dst = min(A, B) dst = min(A, B) 1 1 1 4-102 dst = –src dst = –src 1 1 1 4-121 dst = src << TS dst = norm(src, TS) dst = src << TS dst = norm(src, TS) 1 1 1 4-124 poly(Smem) B = Smem << 16 A = rnd(A(32–16) * T + B) 1 1 3A, 3B 4-128 dst = rnd(src) dst = src + 215 1 1 1 4-144 saturate(src) saturate(src) 1 1 1 4-156 sqdst(Xmem, Ymem) B = B + A(32–16) * A(32–16) A = (Xmem – Ymem) << 16 1 1 7 4-162 Syntax Expression abdst (Xmem, Ymem) † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 2-8 Instruction Set Summary SPRU179C Logical Operations 2.2 Logical Operations This section summarizes the logical operation instructions. Table 2–7 through Table 2–11 list the instructions within the following functional groups: - AND instructions (Table 2–7) OR instructions (Table 2–8 on page 2-10) XOR instructions (Table 2–9 on page 2-10) Shift instructions (Table 2–10 on page 2-11) Test instructions (Table 2–11 on page 2-11) Table 2–7. AND Instructions W† Cycles† Class Page src = src & Smem 1 1 3A, 3B 4-11 dst = src & #lk [ << SHFT ] dst &= #lk [ << SHFT ] dst = src & #lk << SHFT 2 2 2 4-11 dst = src & #lk << 16 dst &= #lk << 16 dst = src & #lk << 16 2 2 2 4-11 dst = dst & src [ << SHIFT ] dst &= src [ << SHIFT ] dst = dst & src << SHIFT 1 1 1 4-11 Smem = Smem & #lk Smem &= #lk Smem = Smem & #lk 2 2 18A, 18B 4-13 Syntax Expression src = src & Smem src &= Smem † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. SPRU179C Instruction Set Summary 2-9 Logical Operations Table 2–8. OR Instructions W† Cycles† Class Page src = src | Smem 1 1 3A, 3B 4-125 dst = src | #lk [ << SHFT ] dst |= #lk [ << SHFT ] dst = src | #lk << SHFT 2 2 2 4-125 dst = src | #lk << 16 dst |= #lk << 16 dst = src | #lk << 16 2 2 2 4-125 dst = dst | src [ << SHIFT ] dst |= src [ << SHIFT ] dst = dst | src << SHIFT 1 1 1 4-125 Smem = Smem | #lk Smem |= #lk Smem = Smem | #lk 2 2 18A, 18B 4-127 Syntax Expression src = src | Smem src |= Smem † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Table 2–9. XOR Instructions W† Cycles† Class Page src = src ^ Smem 1 1 3A, 3B 4-205 dst = src ^ #lk [ << SHFT ] dst ^= #lk [ << SHFT ] dst = src ^ #lk << SHFT 2 2 2 4-205 dst = src ^ #lk << 16 dst ^= #lk << 16 dst = src ^ #lk << 16 2 2 2 4-205 dst = dst ^ src [ << SHIFT] dst ^= src [ << SHIFT ] dst = dst ^ src << SHIFT 1 1 1 4-205 Smem = Smem ^ #lk Smem ^= #lk Smem = Smem ^ #lk 2 2 18A, 18B 4-207 Syntax Expression src = src ^ Smem src ^= Smem † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 2-10 Instruction Set Summary SPRU179C Logical Operations Table 2–10. Shift Instructions W† Cycles† Class Syntax Expression Page src = src \\ CARRY Rotate left with carry in 1 1 1 4-145 roltc(src) Rotate left with TC in 1 1 1 4-146 src = src // CARRY Rotate right with carry in 1 1 1 4-147 dst = src <<C SHIFT dst = src << SHIFT {arithmetic shift} 1 1 1 4-157 shiftc(src) if src(31) = src(30) then src = src << 1 1 1 1 4-159 dst = src <<< SHIFT dst = src << SHIFT {logical shift} 1 1 1 4-160 † Values for words (W) and cycles assume the use of DARAM for data. Table 2–11. Test Instructions W† Cycles† Class Page TC = Xmem(15 – bit_code) 1 1 3A 4-21 TC = bitf(Smem, #lk) TC = (Smem && #lk) 2 2 6A, 6B 4-22 TC = bitt(Smem) TC = Smem(15 – T(3–0)) 1 1 3A, 3B 4-23 TC = (Smem == #lk) TC = (Smem == #lk) 2 2 6A, 6B 4-33 TC = (AR0 == ARx) TC = (AR0 > ARx) TC = (AR0 < ARx) TC = (AR0 != ARx) Compare ARx with AR0 1 1 1 4-34 Syntax Expression TC = bit(Xmem, bit_code) † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. SPRU179C Instruction Set Summary 2-11 Program-Control Operations 2.3 Program-Control Operations This section summarizes the program-control instructions. Table 2–12 through Table 2–18 list the instructions within the following functional groups: - Branch instructions (Table 2–12) Call instructions (Table 2–13 on page 2-13) Interrupt instructions (Table 2–14 on page 2-13) Return instructions (Table 2–15 on page 2-14) Repeat instructions (Table 2–16 on page 2-14) Stack-manipulating instructions (Table 2–17 on page 2-15) Miscellaneous program-control instructions (Table 2–18 on page 2-15) Table 2–12. Branch Instructions W† Cycles† Class Page PC = pmad(15–0) 2 4/[2¶] 29A 4-14 goto src dgoto src PC = src(15–0) 1 6/[4¶] 30A 4-15 if (Sind != 0) goto pmad if (Sind != 0) dgoto pmad if (Sind  0) then PC = pmad(15–0) 2 4‡/2§/ [2¶] 29A 4-16 if (cond [ , cond [ , cond ] ] ) goto pmad if (cond [ , cond [ , cond ]]) dgoto pmad if (cond(s)) then PC = pmad(15–0) 2 5‡/3§/ [3¶] 31A 4-18 far goto extpmad far dgoto extpmad PC = pmad(15–0), XPC = pmad(22–16) 2 4/[2¶] 29A 4-54 far goto src far dgoto src PC = src(15–0), XPC = src(22–16) 1 6/[4¶] 30A 4-55 Syntax Expression goto pmad dgoto pmad † Values for words (W) and cycles assume the use of DARAM for data. ‡ Conditions true § Condition false ¶ Delayed instruction 2-12 Instruction Set Summary SPRU179C Program-Control Operations Table 2–13. Call Instructions Syntax call src dcall src – –SP, PC + 1[3¶] = TOS, Cycles† Class PC = src(15–0) call pmad dcall pmad W† Expression Page 1 6/[4¶] 30B 4-25 – –SP, PC + 2[4¶] = TOS, PC = pmad(15–0) 2 4/[2§] 29B 4-27 if (cond [ , cond [ , cond ]]) call pmad if (cond [ , cond [ , cond ]]) dcall pmad if (cond(s)) then – –SP, PC + 2[4¶] = TOS, PC = pmad(15–0) 2 5‡/3§/ [3¶] 31B 4-29 far call src far dcall src – –SP, PC + 1[3¶] = TOS, PC = src(15–0), XPC = src(22–16) 1 6/[4¶] 30B 4-56 far call extpmad far dcall extpmad – –SP, PC + 2[4¶] = TOS, PC = pmad(15–0), XPC = pmad(22–16) 2 4/[2¶] 29B 4-58 † Values for words (W) and cycles assume the use of DARAM for data. ‡ Conditions true § Condition false ¶ Delayed instruction Table 2–14. Interrupt Instructions W† Cycles† Class Syntax Expression Page int(K) – –SP, ++ PC = TOS, PC = IPTR(15–7) + K << 2, INTM = 1 1 3 35 4-66 trap(K) – –SP, ++ PC = TOS, PC = IPTR(15–7) + K << 2 1 3 35 4-199 † Values for words (W) and cycles assume the use of DARAM for data. SPRU179C Instruction Set Summary 2-13 Program-Control Operations Table 2–15. Return Instructions Syntax W† Expression Cycles† Class Page 34 4-62 far return far dreturn XPC = TOS, ++ SP, PC = TOS, ++SP 1 6/[4¶] far return_enable far dreturn_enable XPC = TOS, ++ SP, PC = TOS, ++SP, INTM = 0 1 6/[4¶] 34 4-63 if (cond [ , cond [ , cond ] ] ) return if (cond [ , cond [ , cond ]]) dreturn if (cond(s)) then PC = TOS, ++SP 1 5‡/3§/[3¶] 32 4-135 return dreturn PC = TOS, ++SP 1 5/[3¶] 32 4-141 return_enable dreturn_enable PC = TOS, ++SP, INTM = 0 1 5/[3¶] 32 4-142 return_fast dreturn_fast PC = RTN, ++SP, INTM = 0 1 3/[1¶] 33 4-143 † Values for words (W) and cycles assume the use of DARAM for data. ‡ Conditions true § Condition false ¶ Delayed instruction Table 2–16. Repeat Instructions W† Cycles† Class Page Repeat single, RC = Smem 1 3 5A, 5B 4-148 repeat(#K) Repeat single, RC = #K 1 1 1 4-148 repeat(#lk) Repeat single, RC = #lk 2 2 2 4-148 blockrepeat(pmad) dblockrepeat(pmad) Repeat block, RSA = PC + 2[4¶], REA = pmad, BRAF = 1 2 4/[2¶] 29A 4-150 repeat(#lk), dst = 0 Repeat single, RC = #lk, dst = 0 2 2 2 4-152 Syntax Expression repeat(Smem) † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. ¶ Delayed instruction 2-14 Instruction Set Summary SPRU179C Program-Control Operations Table 2–17. Stack-Manipulating Instructions Syntax Expression W† Cycles† Class Page SP = SP + K SP + = K SP = SP + K 1 1 1 4-61 Smem = pop() Smem = TOS, ++SP 1 1 17A, 17B 4-129 MMR = pop() mmr(MMR) = pop() MMR = TOS, ++SP 1 1 17A 4-130 push(Smem) – –SP, Smem = TOS 1 1 16A, 16B 4-133 push(MMR) push(mmr(MMR)) – –SP, MMR = TOS 1 1 16A 4-134 † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Table 2–18. Miscellaneous Program-Control Instructions W† Cycles† Class Syntax Expression Page idle(K) idle(K) 1 4 36 4-64 mar(Smem) If CMPT = 0, then modify ARx If CMPT = 1 and ARx  AR0, then modify ARx, ARP = x If CMPT = 1 and ARx = AR0, then modify AR(ARP) 1 1 1, 2 4-94 nop no operation 1 1 1 4-123 reset software reset 1 3 35 4-140 SBIT = 0 ST(N, SBIT) = 0 STN (SBIT) = 0 1 1 1 4-153 SBIT = 1 ST(N, SBIT) = 1 STN (SBIT) = 1 1 1 1 4-170 if (cond [ , cond [ , cond ]]) execute(n) If (cond(s)) then execute the next n instructions; n = 1 or 2 1 1 1 4-202 † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. SPRU179C Instruction Set Summary 2-15 Load and Store Operations 2.4 Load and Store Operations This section summarizes the load and store instructions. Table 2–19 through Table 2–26 list the instructions within the following functional groups: - Load instructions (Table 2–19) Store instructions (Table 2–20 on page 2-18) Conditional store instructions (Table 2–21 on page 2-18) Parallel load and store instructions (Table 2–22 on page 2-19) Parallel load and multiply instructions (Table 2–23 on page 2-19) Parallel store and add/subtract instructions (Table 2–24 on page 2-19) Parallel store and multiply instructions (Table 2–25 on page 2-20) Miscellaneous load-type and store-type instructions (Table 2–26 on page 2-21) Table 2–19. Load Instructions Syntax Expression W† Cycles† Class Page dst = dbl(Lmem) dst = dual(Lmem) dst = Lmem 1 1 9A, 9B 4-42 dst = Smem dst = Smem 1 1 3A, 3B 4-67 dst = Smem << TS dst = Smem << TS 1 1 3A, 3B 4-67 dst = Smem << 16 dst = Smem << 16 1 1 3A, 3B 4-67 dst = Smem [ << SHIFT ] dst = Smem << SHIFT 2 2 4A, 4B 4-67 dst = Xmem [ << SHFT ] dst = Xmem << SHFT 1 1 3A 4-67 dst = #K dst = #K 1 1 1 4-67 dst = #lk [ << SHFT ] dst = #lk << SHFT 2 2 2 4-67 dst = #lk << 16 dst = #lk << 16 2 2 2 4-67 dst = src << ASM dst = src << ASM 1 1 1 4-67 dst = src [ << SHIFT ] dst = src << SHIFT 1 1 1 4-67 T = Smem T = Smem 1 1 3A, 3B 4-71 DP = Smem DP = Smem(8–0) 1 3 5A, 5B 4-71 † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem or Smem. 2-16 Instruction Set Summary SPRU179C Load and Store Operations Table 2–19. Load Instructions (Continued) W† Cycles† Class Page DP = #k9 1 1 1 4-71 ASM = #k5 ASM = #k5 1 1 1 4-71 ARP = #k3 ARP = #k3 1 1 1 4-71 ASM = Smem ASM = Smem(4–0) 1 1 3A, 3B 4-71 dst = MMR dst = mmr(MMR) dst = MMR 1 1 3A 4-74 dst = rnd(Smem) dst = rnd(Smem) 1 1 3A, 3B 4-79 dst = uns(Smem) dst = uns(Smem) 1 1 3A, 3B 4-80 ltd(Smem) T = Smem, (Smem + 1) = Smem 1 1 24A, 24B 4-82 Syntax Expression DP = #k9 † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem or Smem. SPRU179C Instruction Set Summary 2-17 Load and Store Operations Table 2–20. Store Instructions Syntax Expression W† Cycles† Class Page dbl(Lmem) = src dual(Lmem) = src Lmem = src 1 2 13A, 13B 4-48 Smem = T Smem = T 1 1 10A, 10B 4-171 Smem = TRN Smem = TRN 1 1 10A, 10B 4-171 Smem = #lk Smem = #lk 2 2 12A, 12B 4-171 Smem = hi(src) Smem = src << –16 1 1 10A, 10B 4-173 Smem = hi(src) << ASM Smem = src << (ASM – 16) 1 1 10A, 10B 4-173 Xmem = hi(src) << SHFT Xmem = src << (SHFT – 16) 1 1 10A 4-173 Smem = hi(src) << SHIFT Smem = src << (SHIFT – 16) 2 2 11A, 11B 4-173 Smem = src Smem = src 1 1 10A, 10B 4-176 Smem = src << ASM Smem = src << ASM 1 1 10A, 10B 4-176 Xmem = src << SHFT Xmem = src << SHFT 1 1 10A, 10B 4-176 Smem = src << SHIFT Smem = src << SHIFT 2 2 11A, 11B 4-176 MMR = src mmr(MMR) = src MMR = src 1 1 10A 4-179 MMR = #lk mmr(MMR) = #lk MMR = #lk 2 2 12A 4-180 † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem or Smem. Table 2–21. Conditional Store Instructions W† Cycles† Class Page If src(31–16) > src(15–0) then Smem = src(31–16) If src(31–16) v src(15–0) then Smem = src(15–0) 1 1 10A, 10B 4-35 if (cond) Xmem = hi(src) << ASM If (cond) Xmem = src << (ASM – 16) 1 1 15 4-154 if (cond) Xmem = BRC If (cond) Xmem = BRC 1 1 15 4-169 if (cond) Xmem = T If (cond) Xmem = T 1 1 15 4-190 Syntax Expression cmps(src, Smem) † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 2-18 Instruction Set Summary SPRU179C Load and Store Operations Table 2–22. Parallel Load and Store Instructions W† Cycles† Class Syntax Expression Page Ymem = hi(src) [ << ASM ] || dst = Xmem << 16 Ymem = src << (ASM * 16) || dst = Xmem << 16 1 1 14 4-182 Ymem = hi(src) [ << ASM ] || T = Xmem Ymem = src << (ASM – 16) || T = Xmem 1 1 14 4-182 † Values for words (W) and cycles assume the use of DARAM for data. Table 2–23. Parallel Load and Multiply Instructions W† Cycles† Class Syntax Expression Page dst = Xmem [ << 16 ] || dst_ = dst_ + T * Ymem dst = Xmem [ << 16 ] || dst_ + = T * Ymem dst = Xmem << 16 || dst_ = dst_ + T * Ymem 1 1 7 4-75 dst = Xmem [ << 16 ] || dst_ = rnd(dst_ + T * Ymem) dst = Xmem << 16 || dst_ = rnd(dst_ + T * Ymem) 1 1 7 4-75 dst = Xmem [ << 16 ] || dst_ = dst_ – T * Ymem dst = Xmem [ << 16 ] || dst_ – = T * Ymem dst = Xmem << 16 || dst_ = dst_ – T * Ymem 1 1 7 4-77 dst = Xmem [ << 16 ] || dst_ = rnd(dst_ – T * Ymem) dst = Xmem << 16 || dst_ = rnd(dst_ – T * Ymem) 1 1 7 4-77 † Values for words (W) and cycles assume the use of DARAM for data. Table 2–24. Parallel Store and Add/Subtract Instructions W† Cycles† Class Syntax Expression Page Ymem = hi(src) [ << ASM ] || dst = dst_ + Xmem << 16 Ymem = src << (ASM * 16) || dst = dst_ + Xmem << 16 1 1 14 4-181 Ymem = hi(src) [ << ASM ] || dst = Xmem << 16 – dst_ Ymem = src << (ASM – 16) || dst = (Xmem << 16) – dst_ 1 1 14 4-189 † Values for words (W) and cycles assume the use of DARAM for data. SPRU179C Instruction Set Summary 2-19 Load and Store Operations Table 2–25. Parallel Store and Multiply Instructions W† Cycles† Class Syntax Expression Page Ymem = hi(src) [ << ASM ] || dst = dst + T * Xmem Ymem = hi(src) [ << ASM ] || dst + = T * Xmem Ymem = src << (ASM – 16) || dst = dst + T * Xmem 1 1 14 4-184 Ymem = hi(src) [ << ASM ] || dst = rnd(dst + T * Xmem) Ymem = src << (ASM – 16) || dst = rnd(dst + T * Xmem) 1 1 14 4-184 Ymem = hi(src) [ << ASM ] || dst = dst – T * Xmem Ymem = hi(src) [ << ASM ] || dst – = T * Xmem Ymem = src << (ASM – 16) || dst = dst – T * Xmem 1 1 14 4-186 Ymem = hi(src) [ << ASM ] || dst = rnd(dst – T * Xmem) Ymem = src << (ASM – 16) || dst = rnd(dst – T * Xmem) 1 1 14 4-186 Ymem = hi(src) [ << ASM ] || dst = T * Xmem Ymem = src << (ASM – 16) || dst = T * Xmem 1 1 14 4-188 † Values for words (W) and cycles assume the use of DARAM for data. 2-20 Instruction Set Summary SPRU179C Load and Store Operations Table 2–26. Miscellaneous Load-Type and Store-Type Instructions W† Cycles† Class Page Ymem = Xmem 1 1 14 4-109 data(dmad) = Smem dmad = Smem 2 2 19A, 19B 4-110 MMR = data(dmad) mmr(MMR) = data(dmad) MMR = dmad 2 2 19A 4-112 prog(pmad) = Smem pmad = Smem 2 4 20A, 20B 4-113 Smem = data(dmad) Smem = dmad 2 2 19A, 19B 4-115 data(dmad) = MMR data(dmad) = mmr(MMR) dmad = MMR 2 2 19A 4-117 MMRy = MMRx mmr(MMRy) = mmr(MMRx) MMRy = MMRx 1 1 1 4-118 Smem = prog(pmad) Smem = pmad 2 3 21A, 21B 4-119 Smem = port(PA) Smem = PA 2 2 27A, 27B 4-131 port(PA) = Smem PA = Smem 2 2 28A, 28B 4-132 Smem = prog(A) Smem = A 1 5 25A, 25B 4-138 prog(A) = Smem A = Smem 1 5 26A, 26B 4-200 Syntax Expression Ymem = Xmem † Values for words (W) and cycles assume the use of DARAM for data. Add 1 word and 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. SPRU179C Instruction Set Summary 2-21 Repeating a Single Instruction 2.5 Repeating a Single Instruction The TMS320C54x™ DSP includes repeat instructions that cause the next instruction to be repeated. The number of times for the instruction to be repeated is obtained from an operand of the instruction and is equal to this operand + 1. This value is stored in the 16-bit repeat counter (RC) register. You cannot program the value in the RC register; it is loaded by the repeat instructions only. The maximum number of executions of a given instruction is 65 536. An absolute program or data address is automatically incremented when the single-repeat feature is used. Once a repeat instruction is decoded, all interrupts, including NMI but not RS, are disabled until the completion of the repeat loop. However, the C54x™ DSP does respond to the HOLD signal while executing a repeat loop—the response depends on the value of the HM bit of status register 1 (ST1). The repeat function can be used with some instructions, such as multiply/ accumulate and block moves, to increase the execution speed of these instructions. These multicycle instructions (Table 2–27) effectively become single-cycle instructions after the first iteration of a repeat instruction. Table 2–27. Multicycle Instructions That Become Single-Cycle Instructions When Repeated ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á # Cycles† Instruction Description firs Symmetrical FIR filter 3 macd Multiply and move result in accumulator with delay 3 macp Multiply and move result in accumulator 3 data(dmad) = Smem Data-to-data move 2 MMR = data(dmad) Data-to-MMR move 2 prog(pmad) = Smem Data-to-program move 4 Smem = data(dmad) Data-to-data move 2 data(dmad) = MMR MMR-to-data move 2 Smem = prog(pmad) Program-to-data move 3 Smem = prog(A) Read from program-memory to data memory 5 prog(A) = Smem Write data memory to program memory 5 † Number of cycles when instruction is not repeated 2-22 Instruction Set Summary SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C Instruction Set Summary Instruction Smem = Smem + #lk Add long constant to data memory Smem = Smem & #lk AND data memory with long constant [d]goto pmad Unconditional branch [d]goto src Branch to accumulator address if (Sind != 0) [d]goto pmad Branch on auxiliary register not 0 if (cond [ , cond [ , cond ] ] ) [d]goto pmad Conditional branch [d]call src Call to accumulator address [d]call pmad Unconditional call if (cond [ , cond [ , cond ] ] ) [d]call pmad Conditional call TC = (ARx == AR0) TC = (ARx < AR0) TC = (ARx > AR0) TC = (ARx != AR0) Compare with auxiliary register dbl(Lmem) = src Long word (32-bit) store far [d]goto extpmad Far branch unconditionally far [d]goto src Far branch to location specified by accumulator far [d]call src Far call subroutine at location specified by accumulator far [d]call extpmad Far call unconditionally far [d]return Far return far [d]return_enable Enable interrupts and far return from interrupt idle(K) Idle instructions int(K) Interrupt trap ARP = #k3 Load auxiliary register pointer (ARP) DP = Smem DP = #k9 2-23 Description Load data page pointer (DP) Table 2–28. Nonrepeatable Instructions Single data-memory operand instructions cannot be repeated if a long offset modifier or an absolute address is used (for example, *ARn(lk), *+ARn(lk), *+ARn(lk)% and *(lk)). Instructions listed in Table 2–28 cannot be repeated using repeat instructions. Repeating a Single Instruction 2-24 Instruction Set Summary SPRU179C Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Instruction Description MMRy = MMRx Move memory-mapped register (MMR) to another MMR Smem = Smem | #lk OR data memory with long constant if (cond [ , cond [ , cond ] ] ) [d]return Conditional return reset Software reset [d]return Unconditional return [d]return_enable Return from interrupt [d]return_fast Fast return from interrupt dst = rnd(src) Round accumulator repeat(Smem) Repeat next instruction [d]blockrepeat(pmad) Block repeat repeat(#lk), dst = 0 Repeat next instruction and clear accumulator SBIT = 0 Reset status register bit SBIT = 1 Set status register bit trap(K) Software trap if (cond [ , cond [ , cond ] ] ) execute(n) Conditional execute Smem = Smem ^ #lk XOR data memory with long constant Table 2–28. Nonrepeatable Instructions (Continued) Repeating a Single Instruction Chapter 3 Instruction Classes and Cycles Instructions are classified into several categories, or classes, according to cycles required. This chapter describes the instruction classes. Because a single instruction can have multiple syntaxes and types of execution, it can appear in multiple classes. The tables in this chapter show the number of cycles required for a given TMS320C54x™ DSP instruction to execute in a given memory configuration when executed as a single instruction and when executed in the repeat mode. Tables are also provided for a single data-memory operand access used with a long constant. The column headings in the tables indicate the program source location. These headings are defined as follows: ROM The instruction executes from internal program ROM. SARAM The instruction executes from internal single-access RAM. DARAM The instruction executes from internal dual-access RAM. External The instruction executes from external program memory. If a class of instructions requires memory operand(s), the row divisions in the tables indicate the location(s) of the operand(s). These locations are defined as follows: DARAM The operand is in internal dual-access RAM. SARAM The operand is in internal single-access RAM. DROM The operand is in internal data ROM. PROM The operand is in internal program ROM. External The operand is in external memory. MMR The operand is a memory-mapped register. The number of cycles required for each instruction is given in terms of the processor machine cycles (the CLKOUT period). The additional wait states for program/data memory accesses and I/O accesses are defined as follows: d Data-memory wait states—the number of additional clock cycles the device waits for external data-memory to respond to an access. 3-1 Instruction Classes and Cycles io I/O wait states—the number of additional clock cycles the device waits for an external I/O to respond to an access. n Repetitions—the number of times a repeated instruction is executed. nd Data-memory wait states repeated n times. np Program-memory wait states repeated n times. npd Program-memory wait states repeated n times. p Program-memory wait states—the number of additional clock cycles the device waits for external program memory to respond to an access. pd Program-memory wait states—the number of additional clock cycles the device waits for external program memory to respond to an access as a program data operand. These variables can also use the subscripts src, dst, and code to indicate source, destination, and code, respectively. All reads from external memory take at least one instruction cycle to complete, and all writes to external memory take at least two instruction cycles to complete. These external accesses take longer if additional wait-state cycles are added using the software wait-state generator or the external READY input. However, internal to the CPU all writes to external memory take only one cycle as long as no other access to the external memory is in process at the same time. This is possible because the instruction pipeline takes only one cycle to request an external write access, and the external bus interface unit completes the write access independently. The instruction cycles are based on the following assumptions: - At least five instructions following the current instruction are fetched from the same memory section (internal or external) as the current instruction, except in instructions that cause a program counter (PC) discontinuity, such as a branch or call. - When executing a single instruction, there is no pipeline or bus conflict be- tween the current instruction and any other instruction in the pipeline. The only exception is the conflict between the instruction fetch and the memory read/write access (if any) of the instruction under consideration. - In single-instruction repeat mode, all conflicts caused by the pipelined execution of that instruction are considered. 3-2 Instruction Classes and Cycles SPRU179C Class 1 Class 1 1 word, 1 cycle. No operand, or short-immediate or register operands and no memory operands. H dst = |src| H Syntaxes dst dst src << SHIFT dst = dst + src [ << SHIFT ] dst = dst + src << ASM H dst = –src H nop nop H dst = src << TS d = norm(src, TS) ( TS) dst H dst d = dst & src [ << SHIFT ] SHIFT H dst = ~src H dst = dst | src [ << SHIFT ] H TC = (AR0 == ARx) TC = (AR0 > ARx) (AR0 ARx TC = (AR0 < ARx) TC = (AR0 ! AR ) (AR0 != ARx H dst = rnd(src) H src = src \\ CARRY H roltc(src) H xp( T = ex (src) H src = src // CARRY H SP = SP + K H repeat(#K) H dst = #K dst = src << ASM dst = src [ << SHIFT ] H SBIT = 0 ST (N, SBIT) = 0 H saturate(src) H dst = src <<C SHIFT src <<C SHIFT H shiftc(src) H dst = src <<< SHIFT H dst hi(A) hi(A) dst = hi(A) * hi(A) dst = square(hi(A)) H SBIT = 1 ST (N, SBIT) = 1 H dst = dst – src << SHIFT dst = dst – src << ASM dst src << ASM H DP = #k9 ASM = #k5 ARP = #k3 H H mar(Smem) mar( H dst = src – T * hi(A) dst = rnd(src – T * hi(A)) rnd( hi(A)) H dst = max(A, B) B) H dst = min(A, B) H if (cond [, cond [, cond ] ] ) execute(n) H dst d t = T * hi(A) hi(A) H dst = dst ^ src [ << SHIFT] H SPRU179C dst = src + T * hi(A) dst d = rnd(src + T * hi(A)) d( hi(A)) MMRy MMRy = MMRx mmr(MMRy) = mmr(MMRx) Instruction Classes and Cycles 3-3 Instruction Classes and Cycles SPRU179C Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-4 ROM/SARAM DARAM External n n n+p Program Cycles for a Repeat Execution ROM/SARAM DARAM External 1 1 1+p Program Cycles Cycles for a Single Execution Class 1 Class 2 Class 2 2 words, 2 cycles. Long-immediate operand and no memory operands. dst = src + #lk [ << SHFT ] dst = src + #lk << 16 16 H dst = src | #lk [ << SHFT ] dst = src | #lk << 16 dst = src & #lk [ << SHFT ] src dst = src & #lk << 16 << H repeat(#lk) H repeat(#lk), dst = 0 H dst = #lk [ << SHFT ] dst = #lk << 16 H dst = src – #lk [ << SHFT ] << SHFT src dst = src – #lk << 16 H src dst = src + T * #lk H H mar(Smem) dst = src ^ #lk [ << SHFT ] dst = src ^ #lk << 16 H dst = T * #lk ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles H H Syntaxes Cycles for a Single Execution Program ROM/SARAM DARAM External 2 2 2+2p Cycles for a Repeat Execution Program ROM/SARAM External n+1 SPRU179C DARAM n+1 n+1+2p Instruction Classes and Cycles 3-5 Class 3A Class 3A Syntaxes 1 word, 1 cycle. Single data-memory (Smem or Xmem) read operand or MMR read operand. H src = src + Smem src = src + Smem << TS dt 16 dst = src + Smem << 16 src = src + Xmem << SHFT H B = B – Smem * hi(A) [, T = Smem] H dst = T * Smem dst = rnd(T *Smem) H B = Smem * hi(A) [, T = Smem] Smem hi(A) Smem H dst = T * uns(Smem) H src = src | Smem H poly(Smem) oly(Smem H dst = Smem * Smem [, T = Smem] dst square(Smem dst = square(Smem) [, T = Smem] Smem H src = src + Smem + CARRY H src = src + uns(Smem) H src = src & Smem H TC = bit(X bit(Xmem, bit_code) bit d H ( TC = bitt(Smem) H dst = Smem dst = Smem << TS dst = Smem << 16 dst = Xmem [ << SHFT ] H src = src + square(Smem) [, T = Smem] Smem src = src + Smem * Smem [, [, T = Smem] Smem H T = Smem ASM = Smem H H dst = MMR dst = mmr(MMR) mr( src = src – square(Smem) [, T = Smem] Smem src = src – Smem * Smem [, T = Smem] H dst = rnd(Smem) H H dst d = uns(S (Smem) H sc src = src + T * Smem c e src = rnd(src + T * Smem) src = src – Smem src = src – Smem << TS src Smem << TS dst = src – Smem << 16 src = src – Xmem << SHFT H src = src – Smem – BORROW H B = B + Smem * hi(A) [, T = Smem] i(A) B = rnd(B + Smem * hi(A)) [, T = Smem] H src subc(Smem, src) H src = src – uns(Smem) src = src – T * Smem src = rnd(src – T * Smem) H src = src ^ Smem H 3-6 Instruction Classes and Cycles SPRU179C Instruction Classes and Cycles 3-7 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM n n, n+1† n+p SARAM n, n+1† n n+p DROM n, n+1† n n+p External n+nd n+nd n+1+nd+p MMR◊ n n n+p Operand Program Cycles for a Repeat Execution † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 1 1, 2† 1+p SARAM 1, 2† 1 1+p DROM 1, 2† 1 1+p External 1+d 1+d 2+d+p MMR◊ 1 1 1+p Operand Cycles Program Cycles for a Single Execution Class 3A Class 3B Class 3B 2 words, 2 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing. H src = src + Smem src = src + Smem << TS d t = src + Smem << 16 dst 16 H src = src + Smem + CARRY H src = src + uns(Smem) H src = src & Smem H bitt( TC = bitt(Smem) H Syntaxes dst = Smem dst = Smem << TS dst Smem << TS dst = Smem << 16 H H src = src + T * Smem src = rnd(src + T * Smem) rnd( Smem H B = B + Smem * hi(A) [, T = Smem] B = rnd(B + Smem * hi(A) ) d(B hi(A) [, T = Smem] H src = src – T * Smem src = rnd(src – T * Smem) H B = B – Smem * hi(A) [, T = Smem] H B = Smem * hi(A) [, T = Smem] H uns dst = T * uns (Smem) H src = src | Smem H poly(Smem) H dst = Smem * Smem [, T = Smem] Smem Smem Smem dst = square(Smem) [, T = Smem] H src = src + square(Smem) [, T = Smem] src = src + Smem * Smem src Smem Smem [, T = Smem] H src = src – square(Smem) [, T = Smem] src = src – Smem * Smem src Smem Smem [, T = Smem] H src = src – Smem src = src – Smem << TS src Smem << dst = src – Smem << 16 H src = src – Smem – BORROW H subc(Smem, src) H src = src – uns(S (Smem) H src = src ^ Smem dst = uns(Smem) ns( H ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles dst = rnd(Smem) dst = T * Smem dst = rnd(T * Smem) Smem T = Smem ASM = Smem H H Cycles for a Single Execution With Long-Offset Modifier Operand Program Smem ROM/SARAM DARAM External DARAM 2 2, 3† 2+2p SARAM 2, 3† 2 2+2p DROM 2, 3† 2 2+2p External 2+d 2+d 3+d+2p MMR◊ 2 2 2+2p † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. 3-8 Instruction Classes and Cycles SPRU179C Instruction Classes and Cycles 3-9 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM n+1 n+1, n+2† n+1+2p SARAM n+1, n+2† n+1 n+1+2p DROM n+1, n+2† n+1 n+1+2p External n+1+nd n+1+nd n+2+nd+2p MMR◊ n+1 n+1 n+1+2p Operand Program Cycles for a Repeat Execution † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 2 2, 3† 2+2p SARAM 2, 3† 2 2+2p DROM 2, 3† 2 2+2p External 2+d 2+d 3+d+2p MMR◊ 2 2 2+2p Operand Cycles Program Cycles for a Single Execution H dst = src + Smem [ << SHIFT ] H Syntaxes Class 4A dst = Smem [ << SHIFT ] H dst = src – Smem [ << SHIFT ] 2 words, 2 cycles. Single data-memory (Smem) read operand. Class 4A Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-10 † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. ROM/SARAM DARAM External DARAM 3 3, 4† 3+3p SARAM 3, 4† 3 3+3p DROM 3, 4† 3 3+3p External 3+d 3+d 4+d+3p MMR◊ 3 3 3+3p Smem Operand Cycles Program Cycles for a Single Execution With Long-Offset Modifier H dst = src + Smem [ << SHIFT ] H Syntaxes Class 4B dst = Smem [ << SHIFT ] H dst = src – Smem [ << SHIFT ] 3 words, 3 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing. Class 4B ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C Instruction Classes and Cycles 3-11 ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 4 4 4+2p SARAM 4 4 4+2p DROM 4 4 4+2p External 4+d 4+d 4+d+2p MMR◊ 4 4 4+2p Operand Program Cycles for a Single Execution With Long-Offset Modifier H H DP = Smem repeat(Smem) 2 words, 4 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing (with DP destination for load instruction). Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles Syntaxes Class 5B ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 3 3 3+p SARAM 3 3 3+p DROM 3 3 3+p External 3+d 3+d 3+d+p MMR◊ 3 3 3+p Operand Cycles Syntaxes Class 5A Program Cycles for a Single Execution H H DP = Smem repeat(Smem) 1 word, 3 cycles. Single data-memory (Smem) read operand (with DP destination for load instruction). Class 5A Class 5A / Class 5B Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-12 † Operand and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM n+1 n+1, n+2† n+1+2p SARAM n+1, n+2† n+1 n+1+2p DROM n+1, n+2† n+1 n+1+2p External n+1+nd n+1+nd n+2+nd+2p MMR◊ n+1 n+1 n+1+2p Operand Program Cycles for a Repeat Execution † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 2 2, 3† 2+2p SARAM 2, 3† 2 2+2p DROM 2, 3† 2 2+2p External 2+d 2+d 3+d+2p MMR◊ 2 2 2+2p Operand Cycles Program Cycles for a Single Execution H TC = bitf(Smem, #lk) H dst = src + Smem * #lk [, T = Smem] H Syntaxes Class 6A TC = (Smem == #lk) H dst = Smem * #lk [, T = Smem] 2 words, 2 cycles. Single data-memory (Smem) read operand and single long-immediate operand. Class 6A Class 6B Class 6B 3 words, 3 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing and single long-immediate operand. TC = bitf(Smem, #lk) H dst = src + Smem * #lk [, T = Smem] TC = (Smem == #lk) H dst = Smem * #lk [, T = Smem] ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles H H Syntaxes Cycles for a Single Execution With Long-Offset Modifier Operand Program Smem ROM/SARAM DARAM External DARAM 3 3, 4† 3+3p SARAM 3, 4† 3 3+3p DROM 3, 4† 3 3+3p External 3+d 3+d 4+d+3p MMR◊ 3 3 3+3p † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. SPRU179C Instruction Classes and Cycles 3-13 Class 7 Class 7 1 word, 1 cycle. Dual data-memory (Xmem and Ymem) read operands. H abdst (Xmem, Ymem) H dst = Xmem << 16 + Ymem << 16 H dst = Xmem [ << 16 ] || dst_ = dst_ + T * Ymem dst = Xmem [ << 16 ] || dst_ = rnd(dst_ + T * Ymem) H Syntaxes dst = Xmem [ << 16 ] || dst = dst_ – T * Ymem dst_ dst Ymem dst = Xmem [ << 16 ] || dst_ = rnd(dst_ – T * Ymem) H 3-14 src = src + uns(Xmem) * Ymem [, T = Xmem] H dst = src – Xmem * Ymem src Xmem Ymem [, T = Xmem] dst = rnd(src – Xmem * Ymem) [, T = Xmem] Xmem H dst = Xmem * Ymem [, T = Xmem] H sqdst(Xmem, Ymem) Ymem H dst = Xmem << 16 – Ymem << 16 lms(Xmem, Ymem) H H dst = src + Xmem * Ymem [, T = Xmem] dst = rnd(src + Xmem * Ymem) [, T = Xmem] Instruction Classes and Cycles SPRU179C Instruction Classes and Cycles 3-15 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block ‡ Two operands and code in same memory block || One operand and code in same memory block when d = 0 p=0 ◊ Add one cycle for peripheral memorymapped access. k Two operands in same memory block when Xmem Ymem ROM/SARAM DARAM External DARAM DARAM 1 1, 2† 1+p SARAM 1, 2† 1, 2† 1+p DROM 1, 2† 1, 2† 1+p External 1+d 1+d, 2|| 2+d+p DARAM 1, 2† 1 1+p SARAM 1, 2†, 3‡ 1, 2† 1+p, 2k DROM 1, 2† 1 1+p External 1+d, 2|| 1+d 2+d+p DARAM 1, 2† 1 1+p SARAM 1, 2† 1, 2† 1+p, 2k DROM 1, 2†, 3‡ 1, 2† 1+p, 2k External 1+d, 2|| 1+d 2+d+p DARAM 1+d 1+d 2+d+p SARAM 1+d, 2|| 1+d 2+d+p DROM 1+d, 2|| 1+d 2+d+p External 2+2d 2+2d 3+2d+p DARAM 1 1 1+p SARAM 1, 2† 1 1+p DROM 1, 2† 1 1+p External 1+d 1+d 2+d+p MMR◊ External DROM SARAM Operand Cycles Program Cycles for a Single Execution Class 7 3-16 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Operand and code in same memory block ‡ Two operands and code in same memory block # Two operands in same memory block || One operand and code in same memory block when d = 0 ◊ Add n cycles for peripheral memorymapped access. Xmem Ymem ROM/SARAM DARAM External DARAM DARAM n n, n+1† n+p SARAM n, n+1† n, n+1† n+p DROM n, n+1† n, n+1† n+p External n+nd n+nd, 1+n|| n+1+nd+p DARAM n, n+1† n n+p SARAM n, n+1†, 2n#, 2n+1‡ n, 2n# n+p, 2n (p = 0)#, 2n–1+p (p ≥ 1)# DROM n, n+1† n n+p External n+nd, n+1|| n+nd n+1+nd+p DARAM n, n+1† n n+p SARAM n, n+1† n n+p DROM n, n+1†, 2n#, 2n+1‡ n, 2n# n+p, 2n (p = 0)#, 2n–1+p (p ≥ 1)# External n+nd, n+1|| n+nd n+1+nd+p n+nd n+nd n+1+nd+p SARAM n+nd, n+1|| n+nd n+1+nd+p DROM n+nd, n+1|| n+nd n+1+nd+p External 2n+2nd 2n+2nd 2n+1+2nd+p DARAM n n n+p SARAM n, n+1† n n+p DROM n, n+1† n n+p External n+nd n+nd n+1+nd+p MMR◊ External DARAM DROM SARAM Operand Program Cycles for a Repeat Execution Class 7 Instruction Classes and Cycles 3-17 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á Á ÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁÁ ÁÁ Á Á Á ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ Á ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Xmem and pmad in same memory block ‡ Xmem and Ymem in same memory block § Ymem and pmad in same memory block ¶ Xmem, Ymem, and pmad in same memory block pmad Xmem Ymem ROM/SARAM DARAM External DARAM DARAM DARAM 3, 4† 3, 4† 3+2p, 4+2p† SARAM/ DROM 3, 4† 3, 4† 3+2p, 4+2p† External 3+d, 4+d† 3+d, 4+d† 3+d+2p, 4+d+2p† 3 3 3+2p SARAM/ DROM 3, 4‡ 3, 4‡ 3+2p, 4+2p‡ External 3+d 3+d 3+d+2p DARAM 3+d 3+d 3+d+2p SARAM/ DROM 3+d 3+d 3+d+2p External 4+2d 4+2d 4+2d+2p DARAM 3 3 3+2p SARAM/ DROM 3, 4§ 3, 4§ 3+2p, 4+2p§ External 3+d 3+d 3+d+2p SARAM/ DARAM DROM External SARAM/ DARAM DROM Operand Cycles Syntaxes Class 8 Program Cycles for a Single Execution H firs(Xmem, Ymem, pmad) 2 words, 3 cycles. Dual data-memory (Xmem and Ymem) read operands and a single program-memory (pmad) operand. Class 8 3-18 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Xmem and pmad in same memory block ‡ Xmem and Ymem in same memory block § Ymem and pmad in same memory block ¶ Xmem, Ymem, and pmad in same memory block DARAM External 3, 4† 3, 4† 3+2p, 4+2p† SARAM/ DROM 3, 4†, 5¶ 3, 4†, 5¶ 3+2p, 4+2p†, 5+2p¶ External 3+d, 4+d† 3+d, 4+d† 3+d+2p, 4+d+2p† DARAM 3+d 3+d 3+2p SARAM/ DROM 3+d, 4+d§ 3+d, 4+d§ 3+2p, 4+d+2p§ External 4+2d 4+2d 4+2d+2p DARAM 3+pd 3+pd 3+pd+2p SARAM/ DROM 3+pd 3+pd 3+pd+2p External 4+pd+d 4+pd+d 4+pd+d+2p 3+pd 3+pd 3+pd+2p SARAM/ DROM 3+pd, 4+pd‡ 3+pd, 4+pd‡ 3+pd+2p, 4+pd+2p‡ External 4+pd+d 4+pd+d 4+pd+d+2p DARAM 4+pd+d 4+pd+d 4+pd+d+2p SARAM/ DROM 4+pd+d 4+pd+d 4+pd+d+2p External External ROM/SARAM 5+pd+2d 5+pd+2d 5+pd+2d +2p SARAM/ DARAM DROM External DARAM External SARAM/ DARAM DROM pmad Xmem Ymem Operand Program Cycles for a Single Execution (Continued) Class 8 SPRU179C Instruction Classes and Cycles 3-19 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁ Á Á Á ÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á ÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ Á ÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á ÁÁÁ Á ÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ Á ÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ Á ÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ Á ÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á ÁÁ Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁ Á ÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ Á ÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Xmem and pmad in same memory block ‡ Xmem and Ymem in same memory block § Ymem and pmad in same memory block ¶ Xmem, Ymem, and pmad in same memory block pmad Xmem Ymem ROM/ SARAM DARAM External DARAM DARAM DARAM n+2, 2n+2† n+2, 2n+2† n+2+2p, 2n+2+2p† SARAM/ DROM n+2, 2n+2† n+2, 2n+2† n+2+2p, 2n+2+2p† External n+2+nd, 2n+2+nd† n+2+nd, 2n+2+nd† n+2+nd+2p, 2n+2+nd +2p† DARAM n+2 n+2 n+2+2p SARAM/ DROM n+2, 2n+2‡ n+2, 2n+2‡ n+2+2p, 2n+2+2p‡ External n+2+nd n+2+nd n+2+nd+2p DARAM n+2+nd n+2+nd n+2+nd+2p SARAM/ DROM n+2+nd n+2+nd n+2+nd+2p External 2n+2+2nd 2n+2+2nd 2n+2+2nd +2p DARAM n+2 n+2 n+2+2p SARAM/ DROM n+2, 2n+2§ n+2, 2n+2§ n+2+2p, 2n+2+2p§ External n+2+nd n+2+nd n+2+nd+2p SARAM/ DARAM DROM External SARAM/ DROM Operand Program Cycles for a Repeat Execution Class 8 3-20 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ Á ÁÁ Á Á Á Á Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁ Á ÁÁ Á Á Á Á Á ÁÁ Á Á Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á Á ÁÁÁÁÁ Á ÁÁ Á Á Á Á Á Á ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁ Á Á Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Xmem and pmad in same memory block ‡ Xmem and Ymem in same memory block § Ymem and pmad in same memory block ¶ Xmem, Ymem, and pmad in same memory block n+2+2p, 2n+2+2p† n+2, 2n+2†, 3n+2¶ n+2, 2n+2†, 3n+2¶ n+2+2p, 2n+2+2p†, 3n+2+2p¶ n+2+nd, 2n+2+nd† n+2+nd, 2n+2+nd† n+2+nd+2p, 2n+2+nd +2p† DARAM n+2+nd n+2+nd n+2+nd n+2+nd, 2n+2+nd§ n+2+nd, 2n+2+nd§ n+2+nd+2p, 2n+2+nd +2p§ 2n+2+2nd 2n+2+2nd 2n+2+2nd +2p DARAM n+2+npd n+2+npd n+2+npd+2p n+2+npd n+2+npd n+2+npd+2p External 2n+2+npd+nd 2n+2+npd+nd 2n+2+npd +nd+2p DARAM n+2+npd n+2+npd n+2+npd+2p SARAM/ DROM n+2+npd, 2n+2+npd‡ n+2+npd, 2n+2+npd‡ n+2+npd+2p, 2n+2+npd +2p‡ External SARAM/ DROM DARAM SARAM/ DROM DARAM External n+2, 2n+2† External External DARAM n+2, 2n+2† SARAM/ DROM External ROM/ SARAM External Xmem Ymem SARAM/ DROM SARAM/ DROM pmad 2n+2+npd+nd 2n+2+npd+nd 2n+2+npd +nd+2p Operand Program Cycles for a Repeat Execution (Continued) Class 8 SPRU179C Instruction Classes and Cycles 3-21 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁ Á ÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Xmem and pmad in same memory block ‡ Xmem and Ymem in same memory block § Ymem and pmad in same memory block ¶ Xmem, Ymem, and pmad in same memory block Xmem Ymem ROM/ SARAM DARAM External External DARAM 2n+2+npd+nd 2n+2+npd+nd 2n+2+npd +nd+2p SARAM/ DROM 2n+2+npd+nd 2n+2+npd+nd 2n+2+npd +nd+2p External pmad 3n+2+npd+2nd 3n+2+npd+2nd 3n+2+npd +2nd+2p Operand Program Cycles for a Repeat Execution (Continued) Class 8 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-22 † Operand and code in same memory block Lmem ROM/SARAM DARAM External DARAM n n, n+1† n+p SARAM n, n+1† n n+p DROM n, n+1† n n+p External 2n+2nd 2n+2nd 1+2n+2nd+p Operand Program Cycles for a Repeat Execution † Operand and code in same memory block Lmem ROM/SARAM DARAM External DARAM 1 1, 2† 1+p SARAM 1, 2† 1 1+p DROM 1, 2† 1 1+p External 2+2d 2+2d 3+2d+p Operand Cycles Program Cycles for a Single Execution H dst = src + dbl(Lmem) dst = src + dual(Lmem) ( H dst = dadst(Lmem, T) H dst dbl(Lmem) d t = dbl(L dst = dual(Lmem) H Syntaxes Class 9A src = dbl(Lmem) – src src = dual(Lmem) – src H dst = dsadt(Lmem, T) H src = src – dbl(Lmem) src dbl(Lmem src = src – dual(Lmem) H dst dbl(Lmem) – T d t = dbl(L dst = dual(Lmem) – T 1 word, 1 cycle. Single long-word data-memory (Lmem) read operand. Class 9A Class 9B Class 9B 2 words, 2 cycles. Single long-word data-memory (Lmem) read operand using longoffset indirect addressing. dst = src + dbl(Lmem) dst = src + dual(Lmem) ( dst = dadst(Lmem, T) H dst dbl(Lmem) d t = dbl(L dst = dual(Lmem) H src = dbl(Lmem) – src src = dual(Lmem) – src H dst = dsadt(Lmem, T) H src = src – dbl(Lmem) src dbl(Lmem src = src – dual(Lmem) H dst dbl(Lmem) – T d t = dbl(L dst = dual(Lmem) – T ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles H H Syntaxes Cycles for a Single Execution With Long-Offset Modifier Operand Program Lmem ROM/SARAM DARAM External DARAM 2 2, 3† 2+2p SARAM 2, 3† 2 2+2p DROM 2, 3† 2 2+2p External 3+2d 3+2d 4+2d+2p † Operand and code in same memory block SPRU179C Instruction Classes and Cycles 3-23 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-24 † Operand and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM n n n+p SARAM n, n+1† n n+p External 2n–1+(n–1)d 2n–1+(n–1)d 2n+2+nd+p MMR◊ n n n+p Operand Program Cycles for a Repeat Execution † Operand and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 1 1 1+p SARAM 1, 2† 1 1+p External 1 1 4+d+p MMR◊ 1 1 1+p Operand Cycles Program Cycles for a Single Execution H cmps(src, Smem) H Smem = T Smem = TRN H Syntaxes Class 10A Smem = hi(src) i( Smem = hi(src) << ASM Xmem = hi(src) << SHFT H Smem = src Smem = src << ASM Xmem = src << SHFT src SHFT H MMR = src mmr(MMR) = src ( 1 word, 1 cycle. Single data-memory (Smem or Xmem) write operand or an MMR write operand. Class 10A Class 10B Class 10B 2 words, 2 cycles. Single data-memory (Smem or Xmem) write operand using longoffset indirect addressing. cmps(src, Smem) Smem = T Smem = TRN Smem TRN H H Smem = hi(src) Smem = hi(src) << ASM Smem = src Smem = src << ASM Xmem = src << SHFT Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles H H Syntaxes Cycles for a Single Execution With Long-Offset Modifier Operand Program Smem ROM/SARAM DARAM External DARAM 2 2 2+2p SARAM 2, 3† 2 2+2p External 2 2 5+d+2p MMR◊ 2 2 2+2p † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. SPRU179C Instruction Classes and Cycles 3-25 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-26 † Operand and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM n+1 n+1 n+1+2p SARAM n+1, n+2† n+1 n+1+2p External 2n+(n–1)d 2n+(n–1)d 2n+3+nd+2p MMR◊ n+1 n+1 n+1+2p Operand Program Cycles for a Repeat Execution † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 2 2 2+2p SARAM 2, 3† 2 2+2p External 2 2 5+d+2p MMR◊ 2 2 2+2p Operand Cycles Syntaxes Program Cycles for a Single Execution H Class 11A Smem = hi(src) << SHIFT H Smem = src << SHIFT 2 words, 2 cycles. Single data-memory (Smem) write operand. Class 11A Instruction Classes and Cycles 3-27 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 3 3 3+3p SARAM 3, 4† 3 3+3p External 3 3 6+d+3p MMR◊ 3 3 3+3p Operand Cycles Syntaxes Class 11B Program Cycles for a Single Execution With Long-Offset Modifier H Smem = hi(src) << SHIFT H Smem = src << SHIFT 3 words, 3 cycles. Single data-memory (Smem) write operand using long-offset indirect addressing. Class 11B Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-28 † Operand and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 2n 2n 2n+2p SARAM 2n, 2n+1† 2n 2n+2p External 2n+(n–1)d 2n+(n–1)d 2n+3+nd+p MMR◊ 2n 2n 2n+2p Operand Program Cycles for a Repeat Execution † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 2 2 2+2p SARAM 2, 3† 2 2+2p External 2 2 5+d+2p MMR◊ 2 2 2+2p Operand Cycles Syntaxes Program Cycles for a Single Execution H Class 12A H Smem = #lk MMR = #lk mmr(MMR) = #lk 2 words, 2 cycles. Single data-memory (Smem) write operand or MMR write operand. Class 12A Instruction Classes and Cycles 3-29 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 3 3 3+3p SARAM 3, 4† 3 3+3p External 3 3 6+d+3p MMR◊ 3 3 3+3p Operand Cycles Syntaxes Class 12B Program Cycles for a Single Execution With Long-Offset Modifier H Smem = #lk 3 words, 3 cycles. Single data-memory (Smem) write operand using long-offset indirect addressing. Class 12B Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-30 † Operand and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Lmem ROM/SARAM DARAM External DARAM 2n 2n 2n+p SARAM 2n, 2n+2† 2n 2n+p External 4n–1+(2n–1)d 4n–1+(2n–1)d 4n+4+2nd+p MMR◊ 2n 2n 2n+p Operand Program Cycles for a Repeat Execution † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Lmem ROM/SARAM DARAM External DARAM 2 2 2+p SARAM 2, 4† 2 2+p External 3+d 3+d 8+2d+p MMR◊ 2 2 2+p Operand Cycles Syntaxes Program Cycles for a Single Execution H Class 13A dbl(Lmem) = src dual(Lmem) = src 1 word, 2 cycles. Single long-word data-memory (Lmem) write operand. Class 13A Instruction Classes and Cycles 3-31 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Lmem ROM/SARAM DARAM External DARAM 3 3 3+2p SARAM 3, 5† 3 3+2p External 4+d 4+d 9+2d+2p MMR◊ 3 3 3+2p Operand Cycles Syntaxes Class 13B Program Cycles for a Single Execution With Long-Offset Modifier H dbl(Lmem) = src dual(Lmem) = src 2 words, 3 cycles. Single long-word data-memory (Lmem) write operand using longoffset indirect addressing. Class 13B ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-32 Instruction Classes and Cycles SPRU179C † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Xmem Ymem ROM/SARAM DARAM External DARAM DARAM 1 1, 2† 1+p SARAM 1, 2† 1, 2† 1+p External 1 1, 2† 4+d+p DARAM 1, 2† 1 1+p SARAM 1, 2†, 3‡ 1 1+p External 1, 2† 1 4+d+p DARAM 1, 2† 1 1+p SARAM 1, 2† 1 1+p External 1, 2† 1 4+d+p DARAM 1+d 1+d 2+d+p SARAM 1+d, 2+d† 1+d 2+d+p External 1+d 1+d 5+2d+p DARAM 1 1, 2† 1+p SARAM 1, 2† 1 1+p External 1 1 4+d+p MMR◊ External DROM SARAM Operand Cycles Program Cycles for a Single Execution H Ymem = hi(src) [ << ASM ] || dst = dst + T * Xmem t t Ymem = hi(src) [ << ASM ] || dst = rnd(dst + T * Xmem) H Ymem = hi(src) [ << ASM ] || dst = Xmem << 16 Ymem hi( Ymem = hi(src) [ << ASM ] << ASM || T = Xmem Ymem = hi(src) [ << ASM ] || dst = Xmem << 16 – dst_ Ymem = hi(src) [ << ASM ] || dst = dst_ + Xmem << 16 16 H Ymem = hi(src) [ << ASM ] || dst = T * Xmem H Ymem = Xmem Ymem = hi(src) [ << ASM ] || dst = dst – T * Xmem Ymem = hi(src) [ << ASM ] ( || dst = rnd(dst – T * Xmem) H H H Syntaxes Class 14 1 word, 1 cycle. Dual data-memory (Xmem and Ymem) read and write operands. Class 14 SPRU179C Instruction Classes and Cycles 3-33 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Operand and code in same memory block ‡ Two operands and code in same memory block # Two operands in same memory block ◊ Add n cycles for peripheral memorymapped access. Xmem Ymem ROM/SARAM DARAM External DARAM DARAM n n, n+1† n+p SARAM n, n+1† n, n+1† n+p External 2n–1+(n–1)d 2n–1+(n–1)d, 2n+(n–1)d† 2n+2+nd+p DARAM n, n+1† n n+p SARAM n, n+1†, 2n#, 2n+1‡ n, 2n# n+p, 2n+p# External 2n–1+(n–1)d, 2n+(n–1)d† 2n–1+(n–1)d, 2n+(n–1)d† 2n+2+nd+p DARAM n, n+1† n, n+1† n+p SARAM n, n+1† n n+p External 2n–1+(n–1)d, 2n+(n–1)d† 2n–1+(n–1)d 2n+2+nd+p DARAM n+nd n+nd n+1+nd+p SARAM n+nd, n+1+nd† n+nd n+1+nd+p External 4n–3+(2n–1)d 4n–3+(2n–1)d 4n+1+2nd+p DARAM n n, 2n† n+p SARAM n, n+1† n n+p External 2n–1+(n–1)d 2n–1+(n–1)d 2n+2+nd+p MMR◊ External DROM SARAM Operand Program Cycles for a Repeat Execution Class 14 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-34 † Operand and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Xmem ROM/SARAM DARAM External DARAM n n n+p SARAM n, n+1† n n+p External 2n–1+(n–1)d 2n–1+(n–1)d 2n+2+nd+p MMR◊ n n n+p Operand Program Cycles for a Repeat Execution † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Xmem ROM/SARAM DARAM External DARAM 1 1 1+p SARAM 1, 2† 1 1+p External 1 1 4+d+p MMR◊ 1 1 1+p Operand Cycles Program Cycles for a Single Execution H if (cond) Xmem = hi(src) << ASM H Syntaxes Class 15 if (cond) Xmem = BRC H if (cond) Xmem = T 1 word, 1 cycle. Single data-memory (Xmem) write operand. Class 15 Instruction Classes and Cycles 3-35 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem Stack ROM/SARAM DARAM External DARAM DARAM 1 1, 2† 1+p SARAM 1, 2† 1, 2† 1+p External 1 1, 2† 4+d+p DARAM 1, 2† 1 1+p SARAM 1, 2†, 3‡ 1 1+p External 1, 2† 1 4+d+p DARAM 1, 2† 1 1+p SARAM 1, 2† 1 1+p External 1, 2† 1 4+d+p DARAM 1+d 1+d 2+d+p SARAM 1+d, 2+d† 1+d 2+d+p External 1+d 1+d 5+2d+p DARAM 1 1, 2† 1+p SARAM 1, 2† 1 1+p External 1 1 4+d+p MMR◊ External DROM SARAM Operand Cycles Syntaxes Class 16A Program Cycles for a Single Execution H H push(Smem) push(MMR) push(mmr(MMR)) 1 word, 1 cycle. Single data-memory (Smem) read operand or MMR read operand, and a stack-memory write operand. Class 16A 3-36 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Operand and code in same memory block ‡ Two operands and code in same memory block # Two operands in same memory block ◊ Add n cycles for peripheral memorymapped access. Smem Stack ROM/SARAM DARAM External DARAM DARAM n n, n+1† n+p SARAM n, n+1† n, n+1† n+p External 2n–1+(n–1)d 2n–1+(n–1)d, 2n+(n–1)d† 2n+2+nd+p DARAM n, n+1† n n+p SARAM n, n+1†, 2n#, 2n+1‡ n, 2n# n+p, 2n+p# External 2n–1+(n–1)d, 2n+(n–1)d† 2n–1+(n–1)d, 2n+(n–1)d† 2n+2+nd+p DARAM n, n+1† n, n+1† n+p SARAM n, n+1† n n+p External 2n–1+(n–1)d, 2n+(n–1)d† 2n–1+(n–1)d 2n+2+nd+p DARAM n+nd n+nd n+1+nd+p SARAM n+nd, n+1+nd† n+nd n+1+nd+p External 4n–3+(2n–1)d 4n–3+(2n–1)d 4n+1+2nd+p DARAM n n, 2n† n+p SARAM n, n+1† n n+p External 2n–1+(n–1)d 2n–1+(n–1)d 2n+2+nd+p MMR◊ External DROM SARAM Operand Program Cycles for a Repeat Execution Class 16A Instruction Classes and Cycles 3-37 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem Stack ROM/SARAM DARAM External DARAM DARAM 2 2, 3† 2+2p SARAM 2, 3† 2, 3† 2+2p External 2 2, 3† 5+d+2p DARAM 2, 3† 2 2+2p SARAM 2, 3†, 4‡ 2 2+2p External 2, 3† 2 5+d+2p DARAM 2, 3† 2 2+2p SARAM 2, 3† 2 2+2p External 2, 3† 2 5+d+2p DARAM 2+d 2+d 3+d+2p SARAM 2+d, 3+d† 2+d 3+d+2p External 2+d 2+d 6+2d+2p DARAM 2 2, 3† 2+2p SARAM 2, 3† 2 2+2p External 2 2 5+d+2p MMR◊ External DROM SARAM Operand Cycles Syntaxes Class 16B Program Cycles for a Single Execution With Long-Offset Modifier H push(Smem) 2 words, 2 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing and a stack-memory write operand. Class 16B Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-38 † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem Stack ROM/SARAM DARAM External DARAM DARAM 1 1, 2† 1+p SARAM 1, 2† 1 1+p DROM 1, 2† 1 1+p External 1+d 1+d 2+d+p MMR◊ 1 1, 2† 1+p DARAM 1, 2† 1, 2† 1+p SARAM 1, 2†, 3‡ 1 1+p DROM 1, 2† 1 1+p External 1+d, 2+d† 1+d 2+d+p MMR◊ 1, 2† 1 1+p DARAM 1 1, 2† 4+d+p SARAM 1, 2† 1 4+d+p DROM 1, 2† 1 4+d+p External 1+d 1+d 5+2d+p MMR◊ 1 1 4+d+p External SARAM Operand Cycles Syntaxes Program Cycles for a Single Execution H Class 17A H Smem = pop() MMR = pop() mmr(MMR) = pop() 1 word, 1 cycle. Single data-memory (Smem) write operand or MMR write operand, and a stack-memory read operand. Class 17A SPRU179C Instruction Classes and Cycles 3-39 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem Stack ROM/SARAM DARAM External DARAM DARAM n n, n+1† n+p SARAM n, n+1† n n+p DROM n, n+1† n, n+1† n+p External n+nd n+nd n+1+nd+p MMR◊ n n, 2n† n+p DARAM n, n+1† n, n+1† n+p SARAM n, n+1†, 2n 2n+1‡ n, 2n n+p, 2n+p DROM n, n+1† n n+p External n+nd, n+1+nd† n+nd n+1+nd+p MMR◊ n, n+1† n n+p DARAM 2n–1+(n–1)d 2n–1+(n–1)d, 2n+(n–1)d† 2n+2+nd+p SARAM 2n–1+(n–1)d, 2n+(n–1)d† 2n–1+(n–1)d, 2n+(n–1)d† 2n+2+nd+p DROM 2n–1+(n–1)d, 2n+(n–1)d† 2n–1+(n–1)d 2n+2+nd+p External 4n–3+((2n–1)d 4n–3+(2n–1)d 4n+1+2nd+p MMR◊ 2n–1+(n–1)d 2n–1+(n–1)d 2n+2+nd+p External SARAM Operand Program Cycles for a Repeat Execution Class 17A Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á Á ÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-40 † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem Stack ROM/SARAM DARAM External DARAM DARAM 2 2, 3† 2+2p SARAM 2, 3† 2 2+2p DROM 2, 3† 2 2+2p External 2+d 2+d 3+d+2p MMR◊ 2 2, 3† 2+2p DARAM 2, 3 2, 3† 2+2p SARAM 2, 3†, 4‡ 2 2+2p DROM 2, 3† 2 2+2p External 2+d, 3+d† 2+d 3+d+2p MMR◊ 2, 3† 2 2+2p DARAM 2 2, 3† 5+d+2p SARAM 2, 3† 2 5+d+2p DROM 2, 3† 2 5+d+2p External 2+d 2+d 6+2d+2p MMR◊ 2 2 5+d+2p External SARAM Operand Cycles Syntaxes Program Cycles for a Single Execution With Long-Offset Modifier H Class 17B Smem = pop() 2 words, 2 cycles. Single data-memory (Smem) write operand using long-offset indirect addressing, and a stack-memory read operand. Class 17B Instruction Classes and Cycles 3-41 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 3 3, 4† 3+3p SARAM 3, 5† 3 3+3p External 3+d 3+d 7+2d+3p MMR◊ 3 3 3+3p Operand Cycles Program Cycles for a Single Execution With Long-Offset Modifier H Smem = Smem + #lk H Smem = Smem | #lk H Smem = Smem & #lk H Smem = Smem ^ #lk 3 words, 3 cycles. Single data-memory (Smem) read and write operand using longoffset indirect addressing. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Syntaxes Class 18B † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem ROM/SARAM DARAM External DARAM 2 2, 3† 2+2p SARAM 2, 4† 2 2+2p External 2+d 2+d 6+2d+2p MMR◊ 2 2 2+2p Operand Cycles Program Cycles for a Single Execution H Smem = Smem + #lk H Smem = Smem | #lk H Syntaxes Class 18A Smem = Smem & #lk H Smem = Smem ^ #lk 2 words, 2 cycles. Single data-memory (Smem) read and write operand. Class 17B Class 18A / Class 18B ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-42 Instruction Classes and Cycles SPRU179C † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem dmad ROM/SARAM DARAM External DARAM DARAM 2 2, 3† 2+2p SARAM 2, 3† 2, 3† 2+2p External 2 2, 3† 5+d+2p MMR◊ 2 2 2+2p DARAM 2, 3† 2 2+2p SARAM 2, 3†, 4‡ 2 2+2p External 2, 3† 2 5+d+2p MMR◊ 2, 3† 2 2+2p DARAM 2, 3‡ 2 2+2p SARAM 2, 3† 2 2+2p External 2, 3† 2 5+d+2p MMR◊ 2, 3† 2 2+2p DARAM 2+d 2+d 3+d+2p SARAM 2+d, 3+d† 2+d 3+d+2p External 2+d 2+d 6+2d+p MMR◊ 2+d 2+d 3+d+2p DARAM 2 2, 3† 2+2p SARAM 2, 3† 2 2+2p External 2 2 5+d+2p MMR◊ 2 2 2+2p MMR◊ External DROM SARAM Operand Cycles Program Cycles for a Single Execution H data(dmad) = Smem H Smem = data(dmad) H Syntaxes Class 19A MMR = data(d d) t (dmad mmr(MMR) = data(dmad) H data(dmad) = MMR MMR data (dmad) = mmr(MMR) 2 words, 2 cycles. Single data-memory (Smem) read operand or MMR read operand, and single data-memory (dmad) write operand; or single data-memory (dmad) read operand, and single data-memory (Smem) write operand or MMR write operand. Class 19A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á Á Á ÁÁ Á Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á Á Á ÁÁ Á Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C Instruction Classes and Cycles 3-43 † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem dmad ROM/SARAM DARAM External DARAM DARAM n+1 n+1, n+2† n+1+2p SARAM n+1, n+2† n+1, n+2† n+1+2p External 2n+(n–1)d 2n+(n–1)d, 2n+1+(n–1)d† 2n+3+nd+2p MMR◊ n+1 n+1 n+1+2p DARAM n+1, n+2† n+1 n+1+2p SARAM 2n, 2n+1†, 2n+2‡ 2n 2n+2p External 2n+(n–1)d, 2n+1+(n–1)d† 2n+(n–1)d 2n+3+nd+2p MMR◊ n+1, n+2† n+1 n+1+2p DARAM n+1, n+2† n+1 n+1+2p SARAM n+1, n+2† n+1 n+1+2p External 2n+(n–1)d, 2n+1+(n–1)d† 2n+(n–1)d 2n+3+nd+2p MMR◊ n+1, n+2† n+1 n+1+2p DARAM n+1+nd n+1+nd n+1+nd+2p SARAM n+1+nd, n+2nd† n+1+nd n+1+nd+2p External 4n–2+(2n–1)d 4n–2+(2n–1)d 4n+2+2nd+2p MMR◊ n+1+nd n+1+nd n+1+nd+2p DARAM n+1 n+1 n+1+2p SARAM n+1, n+2† n+1 n+1+2p External 2n+(n–1)d 2n+(n–1)d 2n+3+nd+2p MMR◊ n+1 n+1 n+1+2p MMR◊ External DROM SARAM Operand Program Cycles for a Repeat Execution Class 19A Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-44 † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem dmad ROM/SARAM DARAM External DARAM DARAM 3 3, 4† 3+3p SARAM 3, 4† 3, 4† 3+3p External 3 3, 4† 6+d+3p MMR◊ 3 3 3+3p DARAM 3, 4† 3 3+3p SARAM 3, 4†, 5‡ 3 3+3p External 3, 4† 3 6+d+3p MMR◊ 3, 4† 3 3+3p DARAM 3, 4‡ 3 3+3p SARAM 3, 4† 3 3+3p External 3, 4† 3 6+d+3p MMR◊ 3, 4† 3 3+3p DARAM 3+d 3+d 4+d+3p SARAM 3+d, 4+d† 3+d 4+d+3p External 3+d 3+d 7+2d+2p MMR◊ 3+d 3+d 4+d+3p External DROM SARAM Operand Cycles Syntaxes Program Cycles for a Single Execution With Long-Offset Modifier H Class 19B H data(dmad) = Smem Smem = data(dmad) 2 words, 2 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing and single data-memory (dmad) write operand, or single datamemory (dmad) read operand and single data-memory (Smem) write operand using long-offset indirect addressing. Class 19B SPRU179C Instruction Classes and Cycles 3-45 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Operand and code in same memory block ‡ Two operands and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem dmad ROM/SARAM DARAM External MMR◊ DARAM 3 3, 4† 3+3p SARAM 3, 4† 3 3+3p External 3 3 6+d+3p MMR◊ 3 3 3+3p Operand Program Cycles for a Single Execution With Long-Offset Modifier (Continued) Class 19B Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-46 † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem pmad ROM/SARAM DARAM External DARAM DARAM 4 4 4+2p SARAM 4 4 4+2p External 4 4 6+pd+2p DARAM 4, 5† 4 4+2p SARAM 4 4 4+2p External 4 4 6+pd+2p DARAM 4, 5† 4 4+2p SARAM 4 4 4+2p External 4 4 6+pd+2p DARAM 4+d 4+d 4+d+2p SARAM 4+d 4+d 4+d+2p External 4+d+pd 4+d+pd 6+d+pd+2p DARAM 4 4 4+2p SARAM 4 4 4+2p External 4 4 6+pd+2p MMR◊ External DROM SARAM Operand Cycles Syntaxes Program Cycles for a Single Execution H Class 20A prog(pmad) = Smem 2 words, 4 cycles. Single data-memory (Smem) read operand and single programmemory (pmad) write operand. Class 20A SPRU179C Instruction Classes and Cycles 3-47 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ # Two operands in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem pmad ROM/SARAM DARAM External DARAM DARAM n+3 n+3 n+3+2p SARAM n+3 n+3 n+3+2p External 2n+2+(n–1)pd 2n+2+(n–1)pd 2n+4+npd+2p DARAM n+3 n+3 n+3+2p SARAM n+3, 2n+2# n+3, 2n+2# n+3+2p, 2n+2+2p# External 2n+2+(n–1)pd 2n+2+(n–1)pd 2n+4+npd+2p DARAM n+3 n+3 n+3+2p SARAM n+3 n+3 n+3+2p External 2n+2+(n–1)pd 2n+2+(n–1)pd 2n+4+npd+2p DARAM n+3+npd n+3+npd n+3+npd+2p SARAM n+3+npd n+3+npd n+3+npd+2p External 4n+nd+npd 4n+nd+npd 4n+2+nd+npd+2p DARAM n+3 n+3 n+3+2p SARAM n+3 n+3 n+3+2p External 2n+2+(n–1)pd 2n+2+(n–1)pd 2n+4+npd+2p MMR◊ External DROM SARAM Operand Program Cycles for a Repeat Execution Class 20A Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ Á ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-48 † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. Smem pmad ROM/SARAM DARAM External DARAM DARAM 5 5 5+3p SARAM 5 5 5+3p External 5 5 7+2pd+3p DARAM 5, 6† 5 5+3p SARAM 5 5 5+3p External 5 5 7+2pd+3p DARAM 5, 6† 5 5+3p SARAM 5 5 5+3p External 5 5 7+2pd+3p DARAM 5+d 5+d 5+d+3p SARAM 5+d 5+d 5+d+3p External 5+d+2pd 5+d+2pd 7+d+2pd+3p DARAM 5 5 5+3p SARAM 5 5 5+3p External 5 5 7+3pd+3p MMR◊ External DROM SARAM Operand Cycles Syntaxes Program Cycles for a Single Execution With Long-Offset Modifier H Class 20B prog(pmad) = Smem 3 words, 5 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing and single program-memory (pmad) write operand. Class 20B Instruction Classes and Cycles 3-49 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C ◊ Add one cycle for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM 3 3 3+2p SARAM 3 3 3+2p External 3 3 6+d+2p MMR◊ 3 3 3+2p DARAM 3 3 3+2p SARAM 3 3 3+2p External 3 3 6+d+2p MMR◊ 3 3 3+2p DARAM 3 3 3+2p SARAM 3 3 3+2p External 3 3 6+d+2p MMR◊ 3 3 3+2p DARAM 3+pd 3+pd 3+pd+2p SARAM 3+pd 3+pd 3+pd+2p External 3+pd 3+pd 6+d+pd+2p MMR◊ 3+pd 3+pd 3+pd+2p External PROM SARAM Operand Cycles Syntaxes Class 21A Program Cycles for a Single Execution H Smem = prog(pmad) 2 words, 3 cycles. Single program-memory (pmad) read operand and single datamemory (Smem) write operand. Class 21A 3-50 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ # Two operands in same memory block ◊ Add n cycles for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM n+2 n+2 n+2+2p SARAM n+2 n+2 n+2+2p External 2n+1+(n–1)d 2n+1+(n–1)d 2n+4+nd+2p MMR◊ n+2 n+2 n+2+2p DARAM n+2 n+2 n+2+2p SARAM n+2, 2n+1# n+2, 2n+1# n+2+2p External 2n+1+(n–1)d 2n+1+(n–1)d 2n+4+nd+2p MMR◊ n+2 n+2 n+2+2p DARAM n+2 n+2 n+2+2p SARAM n+2 n+2 n+2+2p External 2n+1+(n–1)d 2n+1+(n–1)d 2n+4+nd+2p MMR◊ n+2 n+2 n+2+2p DARAM n+2+npd n+2+npd n+2+npd+2p SARAM n+2+npd n+2+npd n+2+npd+2p External 4n–1+(n–1)d +npd 4n–1+(n–1)d +npd 4n+2+nd+npd+2p MMR◊ n+2+npd n+2+npd n+2+npd+2p External PROM SARAM Operand Program Cycles for a Repeat Execution Class 21A Instruction Classes and Cycles 3-51 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C ◊ Add one cycle for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM 4 4 4+3p SARAM 4 4 4+3p External 4 4 7+d+3p MMR◊ 4 4 4+3p DARAM 4 4 4+3p SARAM 4 4 4+3p External 4 4 7+d+3p MMR◊ 4 4 4+3p DARAM 4 4 4+3p SARAM 4 4 4+3p External 4 4 7+d+3p MMR◊ 4 4 4+3p DARAM 4+2pd 4+2pd 4+2pd+3p SARAM 4+2pd 4+2pd 4+2pd+3p External 4+2pd 4+2pd 7+d+2pd+3p MMR◊ 4+2pd 4+2pd 4+2pd+3p External PROM SARAM Operand Cycles Syntaxes Class 21B Program Cycles for a Single Execution With Long-Offset Modifier H Smem = prog(pmad) 3 words, 4 cycles. Single program-memory (pmad) read operand and single datamemory (Smem) write operand using long-offset indirect addressing. Class 21B Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-52 † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM 3 3, 4† 3+2p SARAM 3, 4† 3 3+2p External 3+d 3+d 4+d+2p MMR◊ 3 3 3+2p DARAM 3 3, 4† 3+2p SARAM 3, 4† 3 3+2p External 3+d 3+d 4+d+2p MMR◊ 3 3 3+2p DARAM 3 3, 4† 3+2p SARAM 3, 4† 3 3+2p External 3+d 3+d 4+d+2p MMR◊ 3 3 3+2p DARAM 3+pd 3+pd, 4+pd† 3+pd+2p SARAM 3+pd 3+pd 4+pd+2p External 4+d+pd 4+d+pd 4+d+pd+2p MMR◊ 3+pd 3+pd 3+pd+2p External PROM SARAM Operand Cycles Syntaxes Program Cycles for a Single Execution H Class 22A macp(Smem, pmad, src) 2 words, 3 cycles. Single data-memory (Smem) read operand and single programmemory (pmad) read operand. Class 22A SPRU179C Instruction Classes and Cycles 3-53 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Operand and code in same memory block # Two operands in same memory block ◊ Add n cycles for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM n+2 n+2, n+3† n+2+2p SARAM n+2, n+3† n+2 n+2+2p External n+2+nd n+2+nd n+2+nd+2p MMR◊ n+2 n+2 n+2+2p DARAM n+2 n+2, n+3† n+2+2p SARAM n+2, n+3†, 2n+2# n+2, 2n+2# n+2+2p, 2n+2+2p# External n+2+nd n+2+nd n+2+nd+2p MMR◊ n+2 n+2 n+2+2p DARAM n+2 n+2, n+3† n+2+2p SARAM n+2, n+3† n+2 n+2+2p External n+2+nd n+2+nd n+2+nd+2p MMR◊ n+2 n+2 n+2+2p DARAM n+2+npd n+2+npd, n+3+npd† n+2+npd+2p SARAM n+2+npd n+2+npd n+3+npd+2p External 2n+2+nd+npd 2n+2+nd+npd 2n+2+nd+npd +2p MMR◊ n+2+npd n+2+npd n+2+npd+2p External PROM SARAM Operand Program Cycles for a Repeat Execution Class 22A Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-54 † Operand and code in same memory block ◊ Add one cycle for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM 4 4, 5† 4+3p SARAM 4, 5† 4 4+3p External 4+d 4+d 5+d+3p MMR◊ 4 4 4+3p DARAM 4 4, 5† 4+3p SARAM 4, 5† 4 4+3p External 4+d 4+d 5+d+3p MMR◊ 4 4 4+3p DARAM 4 4, 5† 4+3p SARAM 4, 5† 4 4+3p External 4+d 4+d 5+d+3p MMR◊ 4 4 4+3p DARAM 4+2pd 4+2pd, 5+2pd† 4+2pd+3p SARAM 4+2pd 4+2pd 5+2pd+3p External 5+d+2pd 5+d+2pd 5+d+2pd+3p MMR◊ 4+2pd 4+2pd 4+2pd+3p External PROM SARAM Operand Cycles Syntaxes Program Cycles for a Single Execution With Long-Offset Modifier H Class 22B macp(Smem, pmad, src) 3 words, 4 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing and single program-memory (pmad) read operand. Class 22B Instruction Classes and Cycles 3-55 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block # Two operands in same memory block ◊ Add one cycle for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM 3, 4# 3, 4# 3+2p, 4+2p# SARAM 3, 4† 3, 4† 3+2p External 3+d 3+d 6+2d+2p MMR◊ 3 3 3+2p DARAM 3, 4† 3 3+2p SARAM 3, 4# 3, 4# 3+2p, 4+2p# External 3+d 3+d 6+2d+2p MMR◊ 3 3 3+2p DARAM 3 3 3+2p SARAM 3, 4† 3 3+2p External 3+d 3+d 6+2d+2p MMR◊ 3 3 3+2p DARAM 3+pd 3+pd 3+pd+2p SARAM 3+pd 3+pd 3+pd+2p External 4+d+pd 4+d+pd 7+d+pd+2p MMR◊ 3+pd 3+pd 4+pd+2p External PROM SARAM Operand Cycles Syntaxes Class 23A Program Cycles for a Single Execution H macd(Smem, pmad, src) 2 words, 3 cycles. Single data-memory (Smem) read operand, single data-memory (Smem) write operand, and single program-memory (pmad) read operand. Class 23A 3-56 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁ Á Á Á ÁÁ Á Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ † Operand and code in same memory block # Two operands in same memory block ◊ Add one cycle for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM n+2, 2n+2# n+2, 2n+2# n+2+2p, 2n+2+2p# SARAM n+2, n+3† n+2, n+3† n+2+2p External 4n+1+2nd 4n+1+2nd 4n+2+2nd+2p MMR◊ n+2 n+2 n+2+2p DARAM n+2, n+3† n+2 n+2+2p SARAM n+2, 2n+2# n+2, 2n+2# n+2+2p, 2n+2+2p# External 4n+1+2nd 4n+1+2nd 4n+2+2nd+2p MMR◊ n+2 n+2 n+2+2p DARAM n+2 n+2 n+2+2p SARAM n+2, n+3† n+2 n+2+2p External 4n+1+2nd 4n+1+2nd 4n+2+2nd+2p MMR◊ n+2 n+2 n+2+2p DARAM n+2+npd n+2+npd, n+3+npd† n+2+npd+2p SARAM n+2+npd n+2+npd n+2+npd+2p External 5n–1+nd+npd 5n–1+nd+npd 5n+2+nd+npd +2p MMR◊ n+2+npd n+2+npd 4n+3+npd+2p External PROM SARAM Operand Program Cycles for a Repeat Execution Class 23A Instruction Classes and Cycles 3-57 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block # Two operands in same memory block ◊ Add one cycle for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM 4, 5# 4, 5# 4+3p, 5+3p# SARAM 4, 5† 4, 5† 4+3p External 4+d 4+d 7+2d+3p MMR◊ 4 4 4+3p DARAM 4, 5† 4 4+3p SARAM 4, 5# 4, 5# 4+3p, 5+3p# External 4+d 4+d 7+2d+3p MMR◊ 4 4 4+3p DARAM 4 4 4+3p SARAM 4, 5† 4 4+3p External 4+d 4+d 7+2d+3p MMR◊ 4 4 4+3p DARAM 4+2pd 4+2pd 4+pd+3p SARAM 4+2pd 4+2pd 4+2pd+3p External 5+d+2pd 5+d+2pd 8+d+2pd+3p MMR◊ 4+2pd 4+2pd 5+2pd+3p External PROM SARAM Operand Cycles Syntaxes Class 23B Program Cycles for a Single Execution With Long-Offset Modifier H macd(Smem, pmad, src) 3 words, 4 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing, single data-memory (Smem) write operand using long-offset indirect addressing, and single program-memory (pmad) read operand. Class 23B ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-58 Instruction Classes and Cycles SPRU179C † Operand and code in same memory block Smem ROM/SARAM DARAM External DARAM 2 2, 3† 2+2p SARAM 2, 4† 2 2+2p External 2+d 2+d 6+2p+2d Operand Program Cycles for a Single Execution With Long-Offset Modifier H H delay(Smem) ltd(Smem) 2 words, 2 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing and single data-memory (Smem) write operand using long-offset indirect addressing. Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles Syntaxes Class 24B † Operand and code in same memory block Smem ROM/SARAM DARAM External DARAM n n, n+1† n+p SARAM 2n–1, 2n+1† 2n–1 2n–1+p External 4n–3+(2n–1)d 4n–3+(2n–1)d 4n+1+p+2nd Operand Program Cycles for a Repeat Execution † Operand and code in same memory block Smem ROM/SARAM DARAM External DARAM 1 1, 2† 1+p SARAM 1, 3† 1 1+p External 1+d 1+d 5+p+2d Operand Program Cycles for a Single Execution Cycles H Syntaxes Class 24A H delay(Smem) ltd(Smem) 1 word, 1 cycle. Single data-memory (Smem) read operand and single data-memory (Smem) write operand. Class 23B / Class 24B Class 24A Instruction Classes and Cycles 3-59 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á Á ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C ◊ Add one cycle for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM 5 5 5+p SARAM 5 5 5+p External 5 5 8+d+p MMR◊ 5 5 5+p DARAM 5 5 5+p SARAM 5 5 5+p External 5 5 8+d+p MMR◊ 5 5 5+p DARAM 5 5 5+p SARAM 5 5 5+p External 5 5 8+d+p MMR◊ 5 5 5+p DARAM 5+pd 5+pd 5+pd+p SARAM 5+pd 5+pd 5+pd+p External 5+pd 5+pd 8+pd+d+p MMR◊ 5+pd 5+pd 5+pd+p External PROM SARAM Operand Cycles Syntaxes Class 25A Program Cycles for a Single Execution H Smem = prog(A) 1 word, 5 cycles. Single program-memory (pmad) read address and single datamemory (Smem) write operand. Class 25A 3-60 Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ # Two operands in same memory block ◊ Add n cycles for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM n+4 n+4 n+4+p SARAM n+4 n+4 n+4+p External 2n+3+(n–1)d 2n+3+(n–1)d 2n+6+nd+np MMR◊ n+4 n+4 n+4+p DARAM n+4 n+4 n+4+p SARAM n+4, 2n+3# n+4, 2n+3# n+4+p, 2n+3+p# External 2n+3+(n–1)d 2n+3+(n–1)d 2n+6+nd+p MMR◊ n+4 n+4 n+4+p DARAM n+4 n+4 n+4+p SARAM n+4 n+4 n+4+p External 2n+3+(n–1)d 2n+3+(n–1)d 2n+6+nd+p MMR◊ n+4 n+4 n+4+p DARAM n+4+npd n+4+npd n+4+npd+p SARAM n+4+npd n+4+npd n+4+npd+p External 4n+1+(n–1)d +npd 4n+1+(n–1)d +npd 4n+4+nd+npd +p MMR◊ n+4+npd n+4+npd n+4+npd+p External PROM SARAM Operand Program Cycles for a Repeat Execution Class 25A Instruction Classes and Cycles 3-61 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á Á ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C ◊ Add one cycle for peripheral memory-mapped access. pmad Smem ROM/SARAM DARAM External DARAM DARAM 6 6 6+2p SARAM 6 6 6+2p External 6 6 9+d+2p MMR◊ 6 6 6+2p DARAM 6 6 6+2p SARAM 6 6 6+2p External 6 6 9+d+2p MMR◊ 6 6 6+2p DARAM 6 6 6+2p SARAM 6 6 6+2p External 6 6 9+d+2p MMR◊ 6 6 6+2p DARAM 6+2pd 6+2pd 6+2pd+2p SARAM 6+2pd 6+2pd 6+2pd+2p External 6+2pd 6+2pd 9+2pd+d+2p MMR◊ 6+2pd 6+2pd 6+2pd+2p External PROM SARAM Operand Cycles Syntaxes Class 25B Program Cycles for a Single Execution With Long-Offset Modifier H Smem = prog(A) 2 words, 6 cycles. Single program-memory (pmad) read address and single datamemory (Smem) write operand using long-offset indirect addressing. Class 25B Instruction Classes and Cycles SPRU179C Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-62 ◊ Add one cycle for peripheral memory-mapped access. Smem pmad ROM/SARAM DARAM External DARAM DARAM 5 5 5+p SARAM 5 5 5+p External 5 5 5+pd+p DARAM 5 5 5+p SARAM 5 5 5+p External 5 5 5+pd+p DARAM 5 5 5+p SARAM 5 5 5+p External 5 5 5+pd+p DARAM 5+pd 5+pd 5+pd+p SARAM 5+pd 5+pd 5+pd+p External 5+d 5+d 7+d+pd+p DARAM 5 5 5+p SARAM 5 5 5+p External 5 5 5+pd+p MMR◊ External DROM SARAM Operand Cycles Syntaxes Program Cycles for a Single Execution H Class 26A prog(A) = Smem 1 word, 5 cycles. Single data-memory (Smem) read operand and single programmemory (pmad) write address. Class 26A SPRU179C Instruction Classes and Cycles 3-63 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ # Two operands in same memory block ◊ Add n cycles for peripheral memory-mapped access. Smem pmad ROM/SARAM DARAM External DARAM DARAM n+4 n+4 n+4+p SARAM n+4 n+4 n+4+p External 2n+3+(n–1)pd 2n+3+(n–1)pd 2n+3+npd+p DARAM n+4 n+4 n+4+p SARAM n+4, 2n+3# n+4, 2n+3# n+4+p, 2n+3+p# External 2n+3+(n–1)pd 2n+3+(n–1)pd 2n+3+npd+p DARAM n+4 n+4 n+4+p SARAM n+4 n+4 n+4+p External 2n+3+(n–1)pd 2n+3+(n–1)pd 2n+3+npd+p DARAM n+4+npd n+4+npd n+4+npd+p SARAM n+4+npd n+4+npd n+4+npd+p External 4n+1+nd +(n–1)pd 4n+1+nd +(n–1)pd 4n+3+nd+npd +p DARAM n+4 n+4 n+4+p SARAM n+4 n+4 n+4+p External 2n+3+(n–1)pd 2n+3+(n–1)pd 2n+3+npd+p MMR◊ External DROM SARAM Operand Program Cycles for a Repeat Execution Class 26A Instruction Classes and Cycles SPRU179C Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁ Á Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-64 ◊ Add one cycle for peripheral memory-mapped access. Smem pmad ROM/SARAM DARAM External DARAM DARAM 6 6 6+2p SARAM 6 6 6+2p External 6 6 6+2pd+2p DARAM 6 6 6+2p SARAM 6 6 6+2p External 6 6 6+2pd+2p DARAM 6 6 6+2p SARAM 6 6 6+2p External 6 6 6+2pd+2p DARAM 6+2pd 6+2pd 6+2pd+2p SARAM 6+2pd 6+2pd 6+2pd+2p External 6+d 6+d 8+d+2pd+2p DARAM 6 6 6+2p SARAM 6 6 6+2p External 6 6 6+2pd+2p MMR◊ External DROM SARAM Operand Cycles Syntaxes Program Cycles for a Single Execution With Long-Offset Modifier H Class 26B prog(A) = Smem 2 words, 6 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing and single program-memory (pmad) write address. Class 26B ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C Instruction Classes and Cycles 3-65 † Operand and code in same memory block Port Smem ROM/SARAM DARAM External External DARAM 4+io 4+io 7+3p+io SARAM 4+io, 5+io† 4+io 7+3p+io External 4+io 4+io 10+3p+d+io Operand Program Cycles for a Single Execution With Long-Offset Modifier H Smem = port(PA) 3 words, 3 cycles. Single I/O port read operand and single data-memory (Smem) write operand using long-offset indirect addressing. Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles Syntaxes Class 27B † Operand and code in same memory block Port Smem ROM/SARAM DARAM External External DARAM 2n+1+nio 2n+1+nio 2n+4+2p+nio SARAM 2n+1+nio, 2n+2+nio† 2n+1+nio 2n+4+2p+nio External 5n–2+nio +(n–1)d 5n–2+nio +(n–1)d 5n+4+2p +nio+nd Operand Program Cycles for a Repeat Execution † Operand and code in same memory block Port Smem ROM/SARAM DARAM External External DARAM 3+io 3+io 6+2p+io SARAM 3+io, 4+io† 3+io 6+2p+io External 3+io 3+io 9+2p+d+io Operand Cycles Syntaxes Class 27A Program Cycles for a Single Execution H Smem = port(PA) 2 words, 2 cycles. Single I/O port read operand and single data-memory (Smem) write operand. Class 26B Class 27A / Class 27B Instruction Classes and Cycles SPRU179C Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-66 † Operand and code in same memory block Port Smem ROM/SARAM DARAM External External DARAM 2n+(n–1)io 2n+(n–1)io, 2n+1+(n–1)io† 2n+4+2p+nio SARAM 2n+(n–1)io, 2n+1+(n–1)io† 2n+(n–1)io 2n+4+2p+nio DROM 2n+(n–1)io, 2n+1+(n–1)io† 2n+(n–1)io 2n+4+2p+nio External 5n–3+nd +(n–1)io 5n–3+nd +(n–1)io 5n+2+2p+nd +nio Operand Program Cycles for a Repeat Execution † Operand and code in same memory block Port Smem ROM/SARAM DARAM External External DARAM 2 2, 3† 6+2p+io SARAM 2, 3† 2 6+2p+io DROM 2, 3† 2 6+2p+io External 2+d 2+d 7+2p+d+io Operand Cycles Syntaxes Program Cycles for a Single Execution H Class 28A port(PA) = Smem 2 words, 2 cycles. Single data-memory (Smem) read operand and single I/O port write operand. Class 28A Instruction Classes and Cycles 3-67 Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block Port Smem ROM/SARAM DARAM External External DARAM 3 3, 4† 7+3p+io SARAM 3, 4† 3 7+3p+io DROM 3, 4† 3 7+3p+io External 3+d 3+d 8+3p+d+io Operand Cycles Syntaxes Class 28B Program Cycles for a Single Execution With Long-Offset Modifier H port(PA) = Smem 3 words, 3 cycles. Single data-memory (Smem) read operand using long-offset indirect addressing and single I/O port write operand. Class 28B ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-68 Instruction Classes and Cycles SPRU179C † Operand and code in same memory block Stack ROM/SARAM DARAM External DARAM 2 2 2+2p SARAM 2, 3† 2 2+2p External 2 2 5+2p+d Operand Program Cycles for a Single Delayed Execution † Operand and code in same memory block Stack ROM/SARAM DARAM External DARAM 4 4 4+4p SARAM 4, 5† 4 4+4p External 4 4 7+4p+d Operand Program Cycles for a Single Execution H H [d]call pmad far [d]call extpmad ÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles Syntaxes Class 29B 2 words, 4 cycles, 2 cycles (delayed). Single program-memory (pmad) operand. ROM/SARAM DARAM External 2 2 2+2p Program Cycles for a Single Delayed Execution ROM/SARAM DARAM External 4 4 4+4p Program Cycles for a Single Execution Cycles H [d]goto pmad H far [d]goto extpmad H Syntaxes Class 29A if (Sind != 0) [d]goto pmad H [d]blockrepeat(pmad) 2 words, 4 cycles, 2 cycles (delayed), 2 cycles (false condition). Single programmemory (pmad) operand. Class 28B / Class 29B Class 29A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C Instruction Classes and Cycles Stack ROM/SARAM DARAM DARAM 4 4 4+p SARAM 4 4 4+p External 4 4 3-69 External 5+p+d Program Cycles for a Single Delayed Execution Stack ROM/SARAM DARAM External DARAM 6 6 6+3p SARAM 6 6 6+3p External 6 6 7+3p+d Program Cycles for a Single Execution H H [d]call src far [d]call src ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles Syntaxes Class 30B 1 word, 6 cycles, 4 cycles (delayed). Single register operand. ROM/SARAM DARAM External 4 4 4+p Program Cycles for a Single Delayed Execution ROM/SARAM DARAM External 6 6 6+3p Program Cycles Syntaxes Class 30A Cycles for a Single Execution H H [d]goto src far [d]goto src 1 word, 6 cycles, 4 cycles (delayed). Single register operand. Class 28B Class 30A / Class 30B Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-70 Condition ROM/SARAM DARAM External True 3 3 3+2p False 3 3 3+2p Program Cycles for a Single Delayed Execution Condition ROM/SARAM DARAM External True 5 5 5+4p False 3 3 3+2p Program Cycles Syntaxes Cycles for a Single Execution H Class 31A if (cond [, cond [, cond ] ] ) [d]goto pmad 2 words, 5 cycles, 3 cycles (delayed). Single program-memory (pmad) operand and short-immediate operands. Class 31A Instruction Classes and Cycles 3-71 Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C † Operand and code in same memory block Stack ROM/SARAM DARAM External DARAM 3 3 3+2p SARAM 3, 4† 3 3+2p External 3 3 6+2p+d Operand Program Cycles for a Single Delayed Execution † Operand and code in same memory block Stack ROM/SARAM DARAM External DARAM 3 3 3+2p SARAM 3, 4† 3 3+2p External 3 3 6+2p+d Operand Program Cycles for a Single False Condition Execution † Operand and code in same memory block Stack ROM/SARAM DARAM External DARAM 5 5 5+4p SARAM 5, 6† 5 5+4p External 5 5 8+4p+d Operand Cycles Syntaxes Class 31B Program Cycles for a Single True Condition Execution H if (cond [, cond [, cond ] ] ) [d]call pmad 2 words, 5 cycles, 3 cycles (delayed), 3 cycles (false condition). Single programmemory (pmad) operand and short-immediate operands. Class 31B Instruction Classes and Cycles SPRU179C ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 3-72 † Operand and code in same memory block ROM/SARAM DARAM External DARAM 3 3, 4† 3+p SARAM 3, 4† 3 3+p External 3+d 3+d 4+d+p Stack Operand Program Cycles for a Single Delayed Execution † Operand and code in same memory block ROM/SARAM DARAM External DARAM 5 5, 6† 5+3p SARAM 5, 6† 5 5+3p External 5+d 5+d 6+d+3p Stack Operand Cycles Program Cycles for a Single Execution H if (cond [, cond [, cond ] ] ) [d]return H Syntaxes Class 32 [d]return H [d]return_enable 1 word, 5 cycles, 3 cycles (delayed), 3 cycles (false condition). No operand, or shortimmediate operands. Class 32 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPRU179C Instruction Classes and Cycles 3-73 † Operand and code in same memory block Stack ROM/SARAM DARAM External DARAM 4 4, 6† 4+p SARAM 4, 6† 4 4+p External 4+2d 4+2d 6+p+2d Program Cycles for a Single Delayed Execution † Operand and code in same memory block ROM/SARAM DARAM External DARAM 6 6, 8† 6+3p SARAM 6, 8† 6 6+3p External 6+2d 6+2d 8+3p+d Stack Program Cycles for a Single Execution H H far [d]return far [d]return_enable Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles Syntaxes Class 34 1 word, 6 cycles, 4 cycles (delayed). No operand. ROM/SARAM DARAM External 1 1 1+p Program Cycles for a Single Delayed Execution ROM/SARAM DARAM External 3 3 3+p Program Cycles Syntaxes Class 33 Cycles for a Single Execution H [d]return_fast 1 word, 3 cycles, 1 cycle (delayed). No operand. Class 32 Class 33 / Class 34 Class 32 / Class 36 Class 35 Class 35 1 word, 3 cycles. No operand or single short-immediate operand. int(K) H reset trap(K) ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cycles H H Syntaxes Cycles for a Single Execution Program ROM/SARAM Syntaxes Cycles 3-74 External 3 Class 36 DARAM 3 3+p 1 word, 4 cycles (minimum). Single short-immediate operand. H idle(K) The number of cycles needed to execute this instruction depends on the idle period. Instruction Classes and Cycles SPRU179C Chapter 4 Assembly Language Instructions This section provides detailed information on the instruction set for the TMS320C54x™ DSP family. The C54x™ DSP instruction set supports numerically intensive signal-processing operations as well as general-purpose applications, such as multiprocessing and high-speed control. See Section 1.1, Instruction Set Symbols and Abbreviations, for definitions of symbols and abbreviations used in the description of assembly language instructions. See Section 1.2, Example Description of Instruction, for a description of the elements in an instruction. See Chapter 2 for a summary of the instruction set. SPRU179C Assembly Language Instructions 4-1 Absolute Distance (abdst) Syntax abdst(Xmem, Ymem) Operands Xmem, Ymem: 15 1 Opcode 14 1 13 1 Dual data-memory operands 12 0 11 0 10 0 9 1 8 1 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (B) + (A(32–16)) ³ B ((Xmem) * (Ymem)) << 16 ³ A Status Bits Affected by OVM, FRCT, and SXM Affects C, OVA, and OVB Description This instruction calculates the absolute value of the distance between two vectors, Xmem and Ymem. The absolute value of accumulator A(32–16) is added to accumulator B. The content of Ymem is subtracted from Xmem, and the result is left-shifted 16 bits and stored in accumulator A. If the fractional mode bit is logical 1 (FRCT = 1), the absolute value is multiplied by 2. Words 1 word Cycles 1 cycle Classes Class 7 (see page 3-14) Example abdst(*AR3+,*AR4+) Before Instruction After Instruction A FF ABCD 0000 A FF FFAB 0000 B 00 0000 0000 B 00 0000 5433 AR3 0100 AR3 0101 AR4 0200 AR4 0201 FRCT 0 FRCT 0 0100h 0055 0100h 0055 0200h 00AA 0200h 00AA Data Memory 4-2 Assembly Language Instructions SPRU179C Absolute Value of Accumulator Syntax dst = |src| Operands src, dst: A (accumulator A) B (accumulator B) Opcode 15 1 Execution (src) ³ dst Status Bits 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 0 3 0 2 1 1 0 0 1 OVM affects this instruction as follows: If OVM = 1, the absolute value of 80 0000 0000h is 00 7FFF FFFFh. If OVM = 0, the absolute value of 80 0000 0000h is 80 0000 0000h. Affects C and OVdst Description This instruction calculates the absolute value of src and loads the value into dst. If the result of the operation is equal to 0, the carry bit, C, is set. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 B = |A| Before Instruction A B Example 2 FF FFFF FFCB After Instruction –53 A FF FFFF FFCB –53 FF FFFF FC18 –1000 B 00 0000 0035 +53 A = |A| Before Instruction A OVM Example 3 03 1234 5678 1 After Instruction A 1 A = |A| Before Instruction A OVM SPRU179C 00 7FFF FFFF OVM 03 1234 5678 0 After Instruction A 03 1234 5678 OVM Assembly Language Instructions 0 4-3 Add to Accumulator Syntax src = src + Smem src += Smem 2: src = src + Smem << TS src += Smem << TS dst = src + Smem << 16 3: dst += Smem << 16 dst = src + Smem [ << SHIFT ] 4: dst += Smem [ << SHIFT ] 5: src = src + Xmem << SHFT src += Xmem << SHFT 6: dst = Xmem << 16 + Ymem << 16 dst = src + #lk [ << SHFT ] 7: dst += #lk [ << SHFT ] dst = src + #lk << 16 8: dst += #lk << 16 dst = dst + src [ << SHIFT ] 9: dst += src [ << SHIFT ] 10: dst = dst + src << ASM dst += src << ASM Operands Smem: Xmem, Ymem: src, dst: Opcode 1: 1: Single data-memory operand Dual data-memory operands A (accumulator A) B (accumulator B) –32 768 v lk v 32 767 –16 v SHIFT v 15 0 v SHFT v 15 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 0 13 0 12 0 11 0 10 1 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 0 13 1 12 1 11 1 10 1 9 S 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 1 13 1 12 0 11 1 10 1 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 0 0 0 0 1 1 S D 0 0 0 S H I F T 2: 3: 4: 4-4 Assembly Language Instructions SPRU179C Add to Accumulator 5: 15 1 14 0 13 0 12 1 11 0 10 0 9 0 8 S 7 X 6 X 5 X 4 X 3 S 2 H 1 F 0 T 15 1 14 0 13 1 12 0 11 0 10 0 9 0 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 6 0 5 0 4 0 3 S 2 H 1 F 0 T 6 1 5 1 4 0 3 0 2 0 1 0 0 0 6: 7: 16-bit constant 8: 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 16-bit constant 9: 15 1 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 0 6 0 5 0 4 S 3 H 2 I 1 F 0 T 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 10: 15 1 (Smem) + (src) ³ src (Smem) << (TS) + (src) ³ src (Smem) << 16 + (src) ³ dst (Smem) [<< SHIFT] + (src) ³ dst (Xmem) << SHFT + (src) ³ src ((Xmem) + (Ymem)) << 16 ³ dst lk << SHFT + (src)³ dst lk << 16 + (src) ³ dst (src or [dst]) + (src) << SHIFT ³ dst (src or [dst]) + (src) << ASM ³ dst Execution 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: Status Bits Affected by SXM and OVM Affects C and OVdst For instruction syntax 3, if the result of the addition generates a carry, the carry bit, C, is set to 1; otherwise, C is not affected. SPRU179C Assembly Language Instructions 4-5 Add to Accumulator Description This instruction adds a 16-bit value to the content of the selected accumulator or to a 16-bit operand Xmem in dual data-memory operand addressing mode. The 16-bit value added is one of the following: - The content of a single data-memory operand (Smem) The content of a dual data-memory operand (Ymem) A 16-bit immediate operand (#lk) The shifted value in src If dst is specified, this instruction stores the result in dst. If no dst is specified, this instruction stores the result in src. Most of the second operands can be shifted. For a left shift: - Low-order bits are cleared - High-order bits are: J J Sign extended if SXM = 1 Cleared if SXM = 0 For a right shift, the high-order bits are: J J Sign extended if SXM = 1 Cleared if SXM = 0 Notes: The following syntaxes are assembled as a different syntax in certain cases. - Syntax 4: If dst = src and SHIFT = 0, then the instruction opcode is assembled as syntax 1. - Syntax 4: If dst = src, SHIFT v 15 and Smem indirect addressing mode is included in Xmem, then the instruction opcode is assembled as syntax 5. - Syntax 5: If SHIFT = 0, the instruction opcode is assembled as syntax 1. Words Syntaxes 1, 2, 3, 5, 6, 9, and 10: 1 word Syntaxes 4, 7, and 8: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1, 2, 3, 5, 6, 9, and 10: 1 cycle Syntaxes 4, 7, and 8: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 4-6 Assembly Language Instructions SPRU179C Add to Accumulator Classes Syntaxes 1, 2, 3, and 5: Class 3A (see page 3-6) Syntaxes 1, 2, and 3: Class 3B (see page 3-8) Syntax 4: Class 4A (see page 3-9) Syntax 4: Class 4B (see page 3-10) Syntax 6: Class 7 (see page 3-14) Syntaxes 7 and 8: Class 2 (see page 3-5) Syntaxes 9 and 10: Class 1 (see page 3-3) Example 1 A = A + *AR3+ << 14 Before Instruction After Instruction A 00 0000 1200 A 00 0540 1200 C 1 C 0 AR3 0100 AR3 0101 SXM 1 SXM 1 Data Memory 0100h Example 2 0100h 1500 B = B + A << –8 Before Instruction A B After Instruction 00 0000 1200 C Example 3 A 00 0000 1200 00 0000 1800 B 00 0000 1812 1 C 0 B = A + #4568 << 8 Before Instruction A B After Instruction 00 0000 1200 C Example 4 1500 A 00 0000 1200 00 0000 1800 B 00 0045 7A00 1 C 0 A = *AR2+ << 16 + *AR2– << 16 ;after accessing the ; operands, AR2 is ; incremented by one. Example 4 shows the same auxiliary register (AR2) with different addressing modes specified for both operands. The mode defined by the Xmod field (*AR2+) is used for addressing. SPRU179C Assembly Language Instructions 4-7 Add to Accumulator With Carry Syntax src = src + Smem + CARRY src += Smem + CARRY Operands Smem: src: Opcode 15 0 14 0 Single data-memory operand A (accumulator A) B (accumulator B) 13 0 12 0 11 0 10 1 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (Smem) + (src) + (C) ³ src Status Bits Affected by OVM, C Affects C and OVsrc Description This instruction adds the 16-bit single data-memory operand Smem and the value of the carry bit (C) to src. This instruction stores the result in src. Sign extension is suppressed regardless of the value of the SXM bit. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example A = A + *+AR2(5) + CARRY Before Instruction After Instruction A 00 0000 0013 A 00 0000 0018 C 1 C 0 AR2 0100 AR2 0105 0004 0105h 0004 Data Memory 0105h 4-8 Assembly Language Instructions SPRU179C Add Long-Immediate Value to Memory Syntax Smem = Smem + #lk Smem += #lk Operands Smem: Single data-memory operand –32 768 v lk v 32 767 Opcode 15 0 14 1 13 1 12 0 11 1 10 0 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution #lk + (Smem) ³ Smem Status Bits Affected by OVM and SXM Affects C and OVA Description This instruction adds the 16-bit single data-memory operand Smem to the 16-bit immediate memory value lk and stores the result in Smem. Note: This instruction is not repeatable. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 18A (see page 3-41) Class 18B (see page 3-41) Example 1 *AR4+ = *AR4+ + #0123Bh Before Instruction AR4 After Instruction 0100 AR4 0101 0004 0100h 123F Data Memory 0100h Example 2 *AR4+ = *AR4+ + #0FFF8h Before Instruction After Instruction OVM 1 OVM 1 SXM 1 SXM 1 AR4 0100 AR4 0101 8007 0100h 8000 Data Memory 0100h SPRU179C Assembly Language Instructions 4-9 Add to Accumulator With Sign-Extension Suppressed Syntax src = src + uns(Smem) src += uns(Smem) Operands Smem: src: Opcode 15 0 14 0 Single data-memory operands A (accumulator A) B (accumulator B) 13 0 12 0 11 0 10 0 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution uns(Smem) + (src) ³ src Status Bits Affected by OVM Affects C and OVsrc Description This instruction adds the 16-bit single data-memory operand Smem to src and stores the result in src. Sign extension is suppressed regardless of the value of the SXM bit. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example B = B + uns(*AR2–) Before Instruction After Instruction B 00 0000 0003 B 00 0000 F009 C x C 0 AR2 0100 AR2 00FF F006 0104h F006 Data Memory 0104h 4-10 Assembly Language Instructions SPRU179C AND With Accumulator Syntax src = src & Smem src &= Smem dst = src & #lk [ << SHFT ] dst &= #lk [ << SHFT ] dst = src & #lk << 16 dst &= #lk << 16 dst = dst & src [ << SHIFT ] dst &= src [ << SHIFT ] 1: 2: 3: 4: Operands Smem: src: Single data-memory operand A (accumulator A) B (accumulator B) –16 v SHIFT v 15 0 v SHFT v 15 0 v lk v 65 535 Opcode 1: 15 0 14 0 13 0 12 1 11 1 10 0 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 6 0 5 1 4 1 3 S 2 H 1 F 0 T 6 1 5 1 4 0 3 0 2 0 1 1 0 1 6 0 5 0 4 S 3 H 2 I 1 F 0 T 2: 16-bit constant 3: 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 16-bit constant 4: 15 1 14 1 13 1 12 1 11 0 10 0 9 S Execution 7 1 1: (Smem) AND (src) ³ src 2: lk << SHFT AND (src)³ dst 3: lk << 16 AND (src)³ dst 4: (dst) AND (src) << SHIFT ³ dst Status Bits 8 D None SPRU179C Assembly Language Instructions 4-11 AND With Accumulator Description This instruction ANDs the following to src: - A 16-bit operand Smem - A 16-bit immediate operand lk - The source or destination accumulator (src or dst) If a shift is specified, this instruction left-shifts the operand before the AND. For a left shift, the low-order bits are cleared and the high-order bits are not sign extended. For a right shift, the high-order bits are not sign extended. Words Syntaxes 1 and 4: 1 word Syntaxes 2 and 3: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1 and 4: 1 cycle Syntaxes 2 and 3: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntax 1: Class 3A (see page 3-6) Syntax 1: Class 3B (see page 3-8) Syntaxes 2 and 3: Class 2 (see page 3-5) Syntax 4: Class 1 (see page 3-3) Example 1 A = *AR3+ & A Before Instruction A AR3 00 00FF 1200 After Instruction A 00 0000 1000 0100 AR3 0101 1500 0100h 1500 Data Memory 0100h Example 2 B = B & A << 3 Before Instruction After Instruction A 4-12 00 0000 1200 A 00 0000 1200 B 00 0000 1800 B 00 0000 1000 Assembly Language Instructions SPRU179C AND Memory With Long Immediate Syntax Smem = Smem & #lk Smem &= #lk Operands Smem: Single data-memory operand 0 v lk v 65 535 Opcode 15 0 14 1 13 1 12 0 11 1 10 0 9 0 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution lk AND (Smem) ³ Smem Status Bits None Description This instruction ANDs the 16-bit single data-memory operand Smem with a 16-bit long constant lk. The result is stored in the data-memory location specified by Smem. Note: This instruction is not repeatable. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 18A (see page 3-41) Class 18B (see page 3-41) Example 1 *AR4+ = *AR4+ & #00FFh Before Instruction AR4 After Instruction 0100 AR4 0101 0444 0100h 0044 Data Memory 0100h Example 2 @4 = @4 & #0101h Before Instruction After Instruction Data Memory 0004h SPRU179C 00 0000 0100 0004h 00 0000 0100 Assembly Language Instructions 4-13 Branch (goto) Unconditionally Syntax [d]goto pmad Operands 0 v pmad v 65 535 Opcode 15 1 14 1 13 1 12 1 11 0 10 0 9 Z 8 0 7 0 6 1 5 1 4 1 3 0 2 0 1 1 0 1 16-bit constant Execution pmad ³ PC Status Bits None Description This instruction passes control to the designated program-memory address (pmad), which can be either a symbolic or numeric address. If the branch is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following the branch instruction is fetched from program memory and executed. Note: This instruction is not repeatable. Words 2 words Cycles 4 cycles 2 cycles (delayed) Classes Class 29A (see page 3-68) Example 1 goto 2000h Before Instruction PC Example 2 1F45 After Instruction PC 2000 dgoto 1000h *AR1+ = *AR1+ & #4444h Before Instruction PC 1F45 After Instruction PC 1000 After the operand has been ANDed with 4444h, the program continues executing from location 1000h. 4-14 Assembly Language Instructions SPRU179C Branch (goto) to Location Specified by Accumulator Syntax [d]goto src Operands src: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 Z 8 S 7 1 6 1 5 1 4 0 3 0 2 0 1 1 0 0 Execution (src(15–0)) ³ PC Status Bits None Description This instruction passes control to the 16-bit address in the low part of src (bits 15–0). If the branch is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following the branch instruction is fetched from program memory and executed. Note: This instruction is not repeatable. Words 1 word Cycles 6 cycles 4 cycles (delayed) Classes Class 30A (see page 3-69) Example 1 goto A Before Instruction A 00 0000 3000 PC Example 2 1F45 After Instruction A 00 0000 3000 PC 3000 dgoto B *AR1+ = *AR1+ & #4444h Before Instruction B PC 00 0000 2000 1F45 After Instruction B 00 0000 2000 PC 2000 After the operand has been ANDed with 4444h value, the program continues executing from location 2000h. SPRU179C Assembly Language Instructions 4-15 Branch (goto) on Auxiliary Register Not Zero Syntax if (Sind != 0) [d]goto pmad Operands Sind: Single indirect addressing operand 0 v pmad v 65 535 Opcode 15 0 14 1 13 1 12 0 11 1 10 1 9 Z 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution If ((ARx) 0 0) Then pmad ³ PC Else (PC) + 2 ³ PC Status Bits None Description This instruction branches to the specified program-memory address (pmad) if the value of the current auxiliary register ARx is not 0. Otherwise, the PC is incremented by 2. If the branch is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following the branch instruction is fetched from program memory and executed. Note: This instruction is not repeatable. Words 2 words Cycles 4 cycles (true condition) 2 cycles (false condition) 2 cycles (delayed) Classes Class 29A (see page 3-68) Example 1 if (*AR3– != 0) goto 2000h Before Instruction After Instruction PC PC 2000 AR3 Example 2 1000 0005 AR3 0004 if (*AR3– != 0) goto 2000h Before Instruction After Instruction PC 4-16 1000 PC 1002 AR3 0000 AR3 FFFF Assembly Language Instructions SPRU179C Branch (goto) on Auxiliary Register Not Zero Example 3 if (*AR3(–1) != 0) dgoto 2000h Before Instruction After Instruction PC Example 4 1000 PC 1003 AR3 0001 AR3 0001 if (*AR3– != 0) dgoto 2000h *AR5+ = *AR5+ & #4444h Before Instruction After Instruction PC 1000 PC 2000 AR3 0004 AR3 0003 After the memory location has been ANDed with 4444h, the program continues executing from location 2000h. SPRU179C Assembly Language Instructions 4-17 Branch (goto) Conditionally Syntax if (cond [, cond [, cond ] ] ) [d]goto pmad Operands 0 v pmad v 65 535 The following table lists the conditions (cond operand) for this instruction. Cond Condition Code Cond Description Condition Code BIO BIO low 0000 0011 NBIO BIO high 0000 0010 C C=1 0000 1100 NC C=0 0000 1000 TC TC = 1 0011 0000 NTC TC = 0 0010 0000 AEQ (A) = 0 0100 0101 BEQ (B) = 0 0100 1101 ANEQ (A) 0 0 0100 0100 BNEQ (B) 0 0 0100 1100 AGT (A) u 0 0100 0110 BGT (B) u 0 0100 1110 AGEQ (A) w 0 0100 0010 BGEQ (B) w 0 0100 1010 ALT (A) t 0 0100 0011 BLT (B) t 0 0100 1011 ALEQ (A) v 0 0100 0111 BLEQ (B) v 0 0100 1111 AOV A overflow 0111 0000 BOV B overflow 0111 1000 ANOV A no overflow 0110 0000 BNOV B no overflow 0110 1000 UNC Opcode Description Unconditional 0000 0000 15 1 14 1 13 1 12 1 11 1 10 0 9 Z 8 0 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C 16-bit constant Execution If (cond(s)) Then pmad ³ PC Else (PC) + 2 ³ PC Status Bits Affects OVA or OVB if OV or NOV is chosen Description This instruction branches to the program-memory address (pmad) if the specified condition(s) is met. The two 1-word instructions or the one 2-word instruction following the branch instruction is fetched from program memory. If the condition(s) is met, the two words following the instruction are flushed from the pipeline and execution begins at pmad. If the condition(s) is not met, the PC is incremented by 2 and the two words following the instruction are executed. 4-18 Assembly Language Instructions SPRU179C Branch (goto) Conditionally If the branch is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction is fetched from program memory and executed. The two words following the delayed instruction have no effect on the conditions being tested. If the condition(s) is met, execution continues at pmad. If the condition(s) is not met, the PC is incremented by 2 and the two words following the delayed instruction are executed. This instruction tests multiple conditions before passing control to another section of the program. This instruction can test the conditions individually or in combination with other conditions. You can combine conditions from only one group as follows: Group1: You can select up to two conditions. Each of these conditions must be from a different category (category A or B); you cannot have two conditions from the same category. For example, you can test EQ and OV at the same time but you cannot test GT and NEQ at the same time. The accumulator must be the same for both conditions; you cannot test conditions for both accumulators with the same instruction. For example, you can test AGT and AOV at the same time, but you cannot test AGT and BOV at the same time. Group 2: You can select up to three conditions. Each of these conditions must be from a different category (category A, B, or C); you cannot have two conditions from the same category. For example, you can test TC, C, and BIO at the same time but you cannot test NTC, C, and NC at the same time. Conditions for This Instruction Group 2 Group 1 Category A Category B Category A Category B Category C EQ OV TC C BIO NEQ NOV NTC NC NBIO LT LEQ GT GEQ Note: This instruction is not repeatable. Words Cycles 2 words 5 cycles (true condition) 3 cycles (false condition) 3 cycles (delayed) Classes Class 31A (see page 3-70) SPRU179C Assembly Language Instructions 4-19 Branch (goto) Conditionally Example 1 if (AGT) goto 2000h Before Instruction A 00 0000 0053 PC Example 2 1000 After Instruction A PC 2000 if (AGT) goto 2000h Before Instruction A FF FFFF FFFF PC Example 3 00 0000 0053 1000 After Instruction A PC FF FFFF FFFF 1002 if (BOV) dgoto 1000h *AR1+ = *AR1+ & #4444h Before Instruction PC OVB 3000 1 After Instruction PC OVB 1000 1 After the memory location is ANDed with 4444h, the branch is taken if the condition (OVB) is met. Otherwise, execution continues at the instruction following this instruction. Example 4 if (TC, NC, BIO) goto 1000h Before Instruction PC C 4-20 Assembly Language Instructions 3000 1 After Instruction PC C 3002 1 SPRU179C Test Bit Syntax TC = bit(Xmem, bit_code) Operands Xmem: Dual data-memory operand 0 v bit_code v 15 Opcode 15 1 14 0 13 0 12 1 11 0 10 1 9 1 8 0 7 X 6 X 5 X 4 X 3 B 2 I 1 T 0 C Execution (Xmem (15 – bit_code)) ³ TC Status Bits Affects TC Description This instruction copies the specified bit of the dual data-memory operand Xmem into the TC bit of status register ST0. The following table lists the bit codes that correspond to each bit in data memory. The bit code corresponds to bit_code and the bit address corresponds to (15 – bit_code). Bit Codes for This Instruction Bit Address (LSB) Bit Code Bit Address Bit Code 0 1111 8 0111 1 1110 9 0110 2 1101 10 0101 3 1100 11 0100 4 1011 12 0011 5 1010 13 0010 6 1001 14 0001 7 1000 15 0000 Words 1 word Cycles 1 cycle Classes Class 3A (see page 3-6) Example TC = bit(*AR5+,15–12) (MSB) ; test bit 3 Before Instruction AR5 TC 0100 0 After Instruction AR5 0101 TC 1 Data Memory 0100h SPRU179C 7688 0100h 7688 Assembly Language Instructions 4-21 Test Bit Field Specified by Immediate Value Syntax TC = bitf(Smem, #lk) Operands Smem: Single data-memory operand 0 v lk v 65 535 Opcode 15 0 14 1 13 1 12 0 11 0 10 0 9 0 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution If ((Smem) AND lk) + 0 Then 0 ³ TC Else 1 ³ TC Status Bits Affects TC Description This instruction tests the specified bit or bits of the data-memory value Smem. If the specified bit (or bits) is 0, the TC bit in status register ST0 is cleared to 0; otherwise, TC is set to 1. The lk constant is a mask for the bit or bits tested. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 6A (see page 3-12) Class 6B (see page 3-13) Example 1 TC = bitf(@5,00FFh) Before Instruction After Instruction TC x TC 0 DP 004 DP 004 Data Memory 0205h Example 2 5400 0205h 5400 TC = bitf(@5,0800h) Before Instruction After Instruction TC x TC 1 DP 004 DP 004 Data Memory 0205h 4-22 Assembly Language Instructions 0F7F 0205h 0F7F SPRU179C Test Bit Specified by T Syntax TC = bitt(Smem) Operands Smem: Opcode 15 0 14 0 Single data-memory operand 13 1 12 1 11 0 10 1 9 0 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (Smem (15 – T(3–0))) ³ TC Status Bits Affects TC Description This instruction copies the specified bit of the data-memory value Smem into the TC bit in status register ST0. The four LSBs of T contain a bit code that specifies which bit is copied. The bit address corresponds to (15 – T(3–0)). The bit code corresponds to the content of T(3–0). Bit Codes for This Instruction Bit Address (LSB) Bit Code Bit Address Bit Code 1111 8 0111 1 1110 9 0110 2 1101 10 0101 3 1100 11 0100 4 1011 12 0011 5 1010 13 0010 6 1001 14 0001 7 Words 0 1000 15 0000 (MSB) 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Class 3A (see page 3-6) Class 3B (see page 3-8) Assembly Language Instructions 4-23 Test Bit Specified by T Example TC = bitt(*AR7+0) Before Instruction After Instruction T C T C TC 0 TC 1 AR0 0008 AR0 0008 AR7 0100 AR7 0108 0008 0100h 0008 Data Memory 0100h 4-24 Assembly Language Instructions SPRU179C Call Subroutine at Location Specified by Accumulator Syntax [d]call src Operands src: Opcode Execution 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 Z 8 S 7 1 6 1 5 1 4 0 3 0 2 0 1 1 0 1 Nondelayed (SP) – 1 ³ SP (PC) + 1 ³ TOS (src(15–0)) ³ PC Delayed (SP) – 1 ³ SP (PC) + 3 ³ TOS (src(15–0)) ³ PC Status Bits None Description This instruction passes control to the 16-bit address in the low part of src (bits 15–0). If the call is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following the call instruction is fetched from program memory and executed. Note: This instruction is not repeatable. Words 1 word Cycles 6 cycles 4 cycles (delayed) Classes Class 30B (see page 3-69) Example 1 call A Before Instruction A 00 0000 3000 After Instruction A 00 0000 3000 PC 0025 PC 3000 SP 1111 SP 1110 1110h 4567 1110h 0026 Data Memory SPRU179C Assembly Language Instructions 4-25 Call Subroutine at Location Specified by Accumulator Example 2 dcall B *AR1+ = *AR1+ & #4444h Before Instruction B 00 0000 2000 After Instruction B 00 0000 2000 PC 0025 PC 2000 SP 1111 SP 1110 1110h 4567 1110h 0028 Data Memory After the memory location has been ANDed with 4444h, the program continues executing from location 2000h. 4-26 Assembly Language Instructions SPRU179C Call Unconditionally Syntax [d]call pmad Operands 0 v pmad v 65 535 Opcode 15 1 14 1 13 1 12 1 11 0 10 0 9 Z 8 0 7 0 6 1 5 1 4 1 3 0 2 1 1 0 0 0 16-bit constant Execution Nondelayed (SP) * 1 ³ SP (PC) ) 2 ³ TOS pmad ³ PC Delayed (SP) * 1 ³ SP (PC) + 4 ³ TOS pmad ³ PC Status Bits None Description This instruction passes control to the specified program-memory address (pmad). The return address is pushed onto the TOS before pmad is loaded into PC. If the call is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following the call instruction is fetched from program memory and executed. Note: This instruction is not repeatable. Words 2 words Cycles 4 cycles 2 cycles (delayed) Classes Class 29B (see page 3-68) SPRU179C Assembly Language Instructions 4-27 Call Unconditionally Example 1 call 3333h Before Instruction After Instruction PC 0025 PC 3333 SP 1111 SP 1110 1110h 4567 1110h 0027 Data Memory Example 2 dcall 1000h @4444h = @4444h & #(*AR1+) Before Instruction After Instruction PC 0025 PC 1000 SP 1111 SP 1110 1110h 4567 1110h 0029 Data Memory After the memory location has been ANDed with 4444h, the program continues executing from location 1000h. 4-28 Assembly Language Instructions SPRU179C Call Conditionally Syntax if (cond [, cond [, cond ] ] ) [d]call pmad Operands 0 v pmad v 65 535 The following table lists the conditions (cond operand) for this instruction. Cond Condition Code Cond Description Condition Code BIO BIO low 0000 0011 NBIO BIO high 0000 0010 C C=1 0000 1100 NC C=0 0000 1000 TC TC = 1 0011 0000 NTC TC = 0 0010 0000 AEQ (A) = 0 0100 0101 BEQ (B) = 0 0100 1101 ANEQ (A) 0 0 0100 0100 BNEQ (B) 0 0 0100 1100 AGT (A) u 0 0100 0110 BGT (B) u 0 0100 1110 AGEQ (A) w 0 0100 0010 BGEQ (B) w 0 0100 1010 ALT (A) t 0 0100 0011 BLT (B) t 0 0100 1011 ALEQ (A) v 0 0100 0111 BLEQ (B) v 0 0100 1111 AOV A overflow 0111 0000 BOV B overflow 0111 1000 ANOV A no overflow 0110 0000 BNOV B no overflow 0110 1000 UNC Opcode Description Unconditional 0000 0000 15 1 14 1 13 1 12 1 11 1 10 0 9 Z 8 1 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C 16-bit constant Execution SPRU179C Nondelayed If (cond(s)) Then (SP) * 1 ³ SP (PC) ) 2 ³ TOS pmad ³ PC Else (PC) + 2 ³ PC Assembly Language Instructions 4-29 Call Conditionally Delayed If (cond(s)) Then (SP) * 1 ³ SP (PC) + 4 ³ TOS pmad ³ PC Else (PC) + 2 ³ PC Status Bits Affects OVA or OVB (if OV or NOV is chosen) Description This instruction passes control to the program-memory address (pmad) if the specified condition(s) is met. The two 1-word instructions or the one 2-word instruction following the call instruction is fetched from program memory. If the condition(s) is met, the two words following the instruction are flushed from the pipeline and execution begins at pmad. If the condition(s) is not met, the PC is incremented by 2 and the two words following the instruction are executed. If the call is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction is fetched from program memory and executed. The two words following the delayed instruction have no effect on the conditions being tested. If the condition(s) is met, execution continues at pmad. If the condition(s) is not met, the PC is incremented by 2 and the two words following the delayed instruction are executed. This instruction tests multiple conditions before passing control to another section of the program. This instruction can test the conditions individually or in combination with other conditions. You can combine conditions from only one group as follows: Group1: Group 2: 4-30 You can select up to two conditions. Each of these conditions must be from a different category (category A or B); you cannot have two conditions from the same category. For example, you can test EQ and OV at the same time but you cannot test GT and NEQ at the same time. The accumulator must be the same for both conditions; you cannot test conditions for both accumulators with the same instruction. For example, you can test AGT and AOV at the same time, but you cannot test AGT and BOV at the same time. You can select up to three conditions. Each of these conditions must be from a different category (category A, B, or C); you cannot have two conditions from the same category. For example, you can test TC, C, and BIO at the same time but you cannot test NTC, C, and NC at the same time. Assembly Language Instructions SPRU179C Call Conditionally Conditions for This Instruction Group 2 Group 1 Category A Category B Category A Category B Category C EQ OV TC C BIO NEQ NOV NTC NC NBIO LT LEQ GT GEQ Note: This instruction is not repeatable. Words 2 words Cycles 5 cycles (true condition) 3 cycles (false condition) 3 cycles (delayed) Classes Class 31B (see page 3-71) Example 1 if (AGT) call 2222h Before Instruction A 00 0000 3000 After Instruction A 00 0000 3000 PC 0025 PC 2222 SP 1111 SP 1110 1110h 4567 1110h 0027 Data Memory Example 2 if (BOV) dcall 1000h *AR1+ = *AR1+ & #4444h Before Instruction PC OVB 0025 1 After Instruction PC OVB 1000 0 SP 1111 SP 1110 1110h 4567 1110h 0029 Data Memory After the memory location has been ANDed with 4444h, the program continues executing from location 1000h. SPRU179C Assembly Language Instructions 4-31 Complement Accumulator Syntax dst = ~src Operands src, dst: Opcode 15 1 14 1 A (accumulator A) B (accumulator B) 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 1 3 0 2 0 1 1 0 1 Execution (src) ³ dst Status Bits None Description This instruction calculates the 1s complement of the content of src (this is a logical inversion). The result is stored in dst, if specified, or src otherwise. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example B = ~A Before Instruction After Instruction A 4-32 FC DFFA AEAA A FC DFFA AEAA B 00 0000 7899 B 03 2005 5155 Assembly Language Instructions SPRU179C Compare Memory With Long Immediate Syntax TC = (Smem == #lk) Operands Smem: Single data-memory operand –32 768 v lk v 32 767 Opcode 15 0 14 1 13 1 12 0 11 0 10 0 9 0 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution If (Smem) + lk Then 1 ³ TC Else 0 ³ TC Status Bits Affects TC Description This instruction compares the 16-bit single data-memory operand Smem to the 16-bit constant lk . If they are equal, TC is set to 1. Otherwise, TC is cleared to 0. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 6A (see page 3-12) Class 6B (see page 3-13) Example TC = (*AR4+ == #0404h) Before Instruction TC AR4 1 After Instruction TC 0 0100 AR4 0101 4444 0100h 4444 Data Memory 0100h SPRU179C Assembly Language Instructions 4-33 Compare Auxiliary Register With AR0 Syntax 1: 2: 3: 4: Operands TC = (AR0 == ARx) TC = (AR0 > ARx) TC = (AR0 < ARx) TC = (AR0 != ARx) ARx: Opcode 15 1 AR0–AR7 14 1 13 1 12 1 11 0 10 1 9 C 8 C 7 1 6 0 5 1 4 0 3 1 2 A 1 R 0 X Execution If (cond) Then 1 ³ TC Else 0 ³ TC Status Bits Affects TC Description This instruction compares the content of the designated auxiliary register (ARx) to the content of AR0 and sets the TC bit according to the comparison. If the condition is true, TC is set to 1. If the condition is false, TC is cleared to 0. All conditions are computed as unsigned operations. Condition Condition Code (CC) EQ 00 Test if (ARx) == (AR0) LT 01 Test if (ARx) < (AR0) GT 10 Test if (ARx) > (AR0) NEQ 11 Test if (ARx) != (AR0) Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example Description TC = (AR0 < AR4) Before Instruction TC 1 After Instruction TC 0 AR0 4-34 FFFF AR0 FFFF AR4 7FFF AR4 7FFF Assembly Language Instructions SPRU179C Compare, Select and Store Maximum (cmps) Syntax cmps(src, Smem) Operands src: Smem: Opcode 15 1 14 0 A (accumulator A) B (accumulator B) Single data-memory operand 13 0 12 0 11 1 10 1 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution If ((src(31–16)) > (src(15–0))) Then (src(31–16)) ³ Smem (TRN) << 1 ³ TRN 0 ³ TRN(0) 0 ³ TC Else (src(15–0)) ³ Smem (TRN) << 1 ³ TRN 1 ³ TRN(0) 1 ³ TC Status Bits Affects TC Description This instruction compares the two 16-bit 2s-complement values located in the high and low parts of src and stores the maximum value in the single datamemory location Smem. If the high part of src (bits 31–16) is greater, a 0 is shifted into the LSB of the transition register (TRN) and the TC bit is cleared to 0. If the low part of src (bits 15–0) is greater, a 1 is shifted into the LSB of TRN and the TC bit is set to 1. This instruction does not follow the standard pipeline operation. The comparison is performed in the read phase; thus, the src value is the value one cycle before the instruction executes. TRN and the TC bit are updated during the execution phase. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Class 10A (see page 3-24) Class 10B (see page 3-25) Assembly Language Instructions 4-35 Compare, Select and Store Maximum (cmps) Example cmps(A,*AR4+) Before Instruction A TC 00 2345 7899 0 After Instruction A TC 00 2345 7899 1 AR4 0100 AR4 0101 TRN 4444 TRN 8889 0000 0100h 7899 Data Memory 0100h 4-36 Assembly Language Instructions SPRU179C Double-Precision/Dual 16-Bit Add to Accumulator Syntax 1: 2: Operands Opcode dst = src + dbl(Lmem) dst += dbl(Lmem) dst = src + dual(Lmem) dst += dual(Lmem) Lmem: src, dst: 15 0 14 1 Long data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 0 10 0 9 S 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution If C16 + 0 Then (Lmem) ) (src) ³ dst Else (Lmem(31–16)) + (src(31–16)) ³ dst(39–16) (Lmem(15–0)) + (src(15–0)) ³ dst(15–0) Status Bits Affected by SXM and OVM (only if C16 = 0) Affects C and OVdst Description This instruction adds the content of src to the 32-bit long data-memory operand Lmem. If a dst is specified, this instruction stores the result in dst. If no dst is specified, this instruction stores the result in src. The value of C16 determines the mode of the instruction: - If C16 = 0, the instruction is executed in double-precision mode. The 40-bit src value is added to the Lmem. The saturation and overflow bits are set according to the result of the operation. - If C16 = 1, the instruction is executed in dual 16-bit mode. The high part of src (bits 31–16) is added to the 16 MSBs of Lmem, and the low part of src (bits 15–0) is added to the 16 LSBs of Lmem. The saturation and overflow bits are not affected in this mode. In this mode, the results are not saturated regardless of the state of the OVM bit. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Lmem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem. Classes SPRU179C Class 9A (see page 3-22) Class 9B (see page 3-23) Assembly Language Instructions 4-37 Double-Precision/Dual 16-Bit Add to Accumulator Example 1 B = A + dbl(*AR3+) Before Instruction After Instruction A 00 5678 8933 A 00 5678 8933 B 00 0000 0000 B 00 6BAC BD89 C16 0 AR3 0100 AR3† C16 0102 0100h 1534 0100h 1534 0101h 3456 0101h 3456 0 Data Memory † Because this instruction is a long-operand instruction, AR3 is incremented by 2 after the execution. Example 2 B = A + dbl(*AR3–) Before Instruction After Instruction A 00 5678 3933 A 00 5678 3933 B 00 0000 0000 B 00 6BAC 6D89 C16 1 C16 1 0100 AR3† 00FE 0100h 1534 0100h 1534 0101h 3456 0101h 3456 AR3 Data Memory † Because this instruction is a long-operand instruction, AR3 is decremented by 2 after the execution. Example 3 B = A + dbl(*AR3–) Before Instruction A 00 5678 3933 B 00 0000 0000 C16 0 After Instruction A 00 5678 3933 B 00 8ACE 4E67 C16 0 0101 AR3† 00FF 0100h 1534 0100h 1534 0101h 3456 0101h 3456 AR3 Data Memory † Because this instruction is a long-operand instruction, AR3 is decremented by 2 after the execution. 4-38 Assembly Language Instructions SPRU179C Double-Precision Load With T Add/Dual 16-Bit Load With T Add/Subtract Syntax dst = dadst(Lmem, T) Operands Lmem: dst: Opcode 15 0 14 1 Long data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 1 10 0 9 1 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution If C16 = 1 Then (Lmem(31–16)) ) (T) ³ dst(39–16) (Lmem(15–0)) * (T) ³ dst(15–0) Else (Lmem) + ((T) + (T) << 16) ³ dst Status Bits Affected by SXM and OVM (only if C16 = 0) Affects C and OVdst Description This instruction adds the content of T to the 32-bit long data-memory operand Lmem. The value of C16 determines the mode of the instruction: - If C16 = 0, the instruction is executed in double-precision mode. Lmem is added to a 32-bit value composed of the content of T concatenated with the content of T left-shifted 16 bits (T <<16 + T). The result is stored in dst. - If C16 = 1, the instruction is executed in dual 16-bit mode. The 16 MSBs of the Lmem are added to the content of T and stored in the upper 24 bits of dst. At the same time, the content of T is subtracted from the 16 LSBs of Lmem. The result is stored in the lower 16 bits of dst. In this mode, the results are not saturated regardless of the state of the OVM bit. Note: This instruction is meaningful only if C16 is set to 1 (dual 16-bit mode). Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Lmem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem. Classes SPRU179C Class 9A (see page 3-22) Class 9B (see page 3-23) Assembly Language Instructions 4-39 Double-Precision Load With T Add/Dual 16-Bit Load With T Add/Subtract Example 1 A = dadst(*AR3–,T) Before Instruction After Instruction A 00 0000 0000 A 00 3879 1111 T 2345 T 2345 C16 1 AR3 0100 AR3† C16 00FE 0100h 1534 0100h 1534 0101h 3456 0101h 3456 1 Data Memory † Because this instruction is a long-operand instruction, AR3 is decremented by 2 after the execution. Example 2 A = dadst(*AR3+,T) Before Instruction After Instruction A 00 0000 0000 A 00 3879 579B T 2345 T 2345 C16 0 C16 0 0100 AR3† 0102 0100h 1534 0100h 1534 0101h 3456 0101h 3456 AR3 Data Memory † Because this instruction is a long-operand instruction, AR3 is incremented by 2 after the execution. 4-40 Assembly Language Instructions SPRU179C Memory Delay Syntax delay(Smem) Operands Smem: Opcode 15 0 Single data-memory operand 14 1 13 0 12 0 11 1 10 1 9 0 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (Smem) ³ Smem ) 1 Status Bits None Description This instruction copies the content of a single data-memory location Smem into the next higher address. When data is copied, the content of the addressed location remains the same. This function is useful for implementing a Z delay in digital signal processing applications. The delay operation is also contained in the load T and insert delay instruction (page 4-82) and the multiply by program memory and accumulate with delay instruction (page 4-89). Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 24A (see page 3-58) Class 24B (see page 3-58) Example delay(*AR3) Before Instruction AR3 After Instruction 0100 AR3 0100 0100h 6CAC 0100h 6CAC 0101h 0000 0101h 6CAC Data Memory SPRU179C Assembly Language Instructions 4-41 Double-Precision/Dual 16-Bit Long-Word Load to Accumulator dst = dbl(Lmem) dst = dual(Lmem) Syntax 1: 2: Operands Lmem: dst: Opcode 15 0 14 1 Long data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 0 10 1 9 1 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution If C16 + 0 Then (Lmem) ³ dst Else (Lmem(31–16)) ³ dst(39–16) (Lmem(15–0)) ³ dst(15–0) Status Bits Affected by SXM Description This instruction loads dst with a 32-bit long operand Lmem. The value of C16 determines the mode of the instruction: - If C16 = 0, the instruction is executed in double-precision mode. Lmem is loaded to dst. - If C16 = 1, the instruction is executed in dual 16-bit mode. The 16 MSBs of Lmem are loaded to the upper 24 bits of dst. At the same time, the 16 LSBs of Lmem are loaded in the lower 16 bits of dst. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Lmem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem. Classes 4-42 Class 9A (see page 3-22) Class 9B (see page 3-23) Assembly Language Instructions SPRU179C Double-Precision/Dual 16-Bit Long-Word Load to Accumulator Example B = dbl(*AR3+) Before Instruction B 00 0000 0000 After Instruction B 00 6CAC BD90 0100 AR3† 0102 0100h 6CAC 0100h 6CAC 0101h BD90 0101h BD90 AR3 Data Memory † Because this instruction is a long-operand instruction, AR3 is incremented by 2 after the execution. SPRU179C Assembly Language Instructions 4-43 Double-Precision/Dual 16-Bit Subtract From Long Word src = dbl(Lmem) – src src = dual(Lmem) – src Syntax 1: 2: Operands Lmem: src: Opcode 15 0 14 1 Long data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 1 10 0 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution If C16 = 0 Then (Lmem) * (src) ³ src Else (Lmem(31–16)) * (src(31–16)) ³ src(39–16) (Lmem(15–0)) * (src(15–0)) ³ src(15–0) Status Bits Affected by SXM and OVM (only if C16 = 0) Affects C and OVsrc Description This instruction subtracts the content of src from the 32-bit long data-memory operand Lmem and stores the result in src. The value of C16 determines the mode of the instruction: - If C16 = 0, the instruction is executed in double-precision mode. The con- tent of src (32 bits) is subtracted from Lmem. The result is stored in src. - If C16 = 1, the instruction is executed in dual 16-bit mode. The high part of src (bits 31–16) is subtracted from the 16 MSBs of Lmem and the result is stored in the high part of src (bits 39–16). At the same time, the low part of src (bits 15–0) is subtracted from the 16 LSBs of Lmem. The result is stored in the low part of src (bits 15–0). In this mode, the results are not saturated regardless of the state of the OVM bit. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Lmem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem. Classes 4-44 Class 9A (see page 3-22) Class 9B (see page 3-23) Assembly Language Instructions SPRU179C Double-Precision/Dual 16-Bit Subtract From Long Word Example 1 A = dbl(*AR3+) – A Before Instruction After Instruction A 00 5678 8933 A FF BEBB AB23 C x C 0 C16 0 AR3 0100 AR3† C16 0102 0100h 1534 0100h 1534 0101h 3456 0101h 3456 0 Data Memory † Because this instruction is a long-operand instruction, AR3 is incremented by 2 after the execution. Example 2 A = dbl(*AR3–) – A Before Instruction After Instruction A 00 5678 3933 A FF BEBC FB23 C 1 C 0 C16 1 C16 1 0100 AR3† 00FE 0100h 1534 0100h 1534 0101h 3456 0101h 3456 AR3 Data Memory † Because this instruction is a long-operand instruction, AR3 is decremented by 2 after the execution. SPRU179C Assembly Language Instructions 4-45 Long-Word Load With T Add/Dual 16-Bit Load With T Subtract/Add Syntax dst = dsadt(Lmem, T) Operands Lmem: dst: Opcode 15 0 14 1 Long data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 1 10 1 9 1 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution If C16 = 1 Then (Lmem(31–16)) * (T) ³ dst(39–16) (Lmem(15–0)) ) (T) ³ dst(15–0) Else (Lmem) – ((T) + (T << 16)) ³ dst Status Bits Affected by SXM and OVM (only if C16 = 0) Affects C and OVdst Description This instruction subtracts/adds the content of T from the 32-bit long datamemory operand Lmem and stores the result in dst. The value of C16 determines the mode of the instruction: - If C16 = 0, the instruction is executed in double-precision mode. A 32-bit value composed of the content of T concatenated with the content of T leftshifted 16 bits (T << 16 + T) is subtracted from Lmem. The result is stored in dst. - If C16 = 1, the instruction is executed in dual 16-bit mode. The content of T is subtracted from the 16 MSBs of Lmem and the result is stored in the high part of dst (bits 39–16). At the same time, the content of T is added to the 16 LSBs of Lmem and the result is stored in the low part of dst (bits 15–0). In this mode, the results are not saturated regardless of the state of the OVM bit. Note: This instruction is meaningful only if C16 is set (dual 16-bit mode). Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Lmem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem. 4-46 Assembly Language Instructions SPRU179C Long-Word Load With T Add/Dual 16-Bit Load With T Subtract/Add Classes Class 9A (see page 3-22) Class 9B (see page 3-23) Example 1 A = dsadt(*AR3+,T) Before Instruction After Instruction A 00 0000 0000 A FF F1EF 1111 T 2345 T 2345 C 0 C 0 C16 0 C16 0 AR3 0100 AR3† 0102 0100h 1534 0100h 1534 0101h 3456 0101h 3456 Data Memory † Because this instruction is a long-operand instruction, AR3 is incremented by 2 after the execution. Example 2 A = dsadt(*AR3–,T) Before Instruction A 00 0000 0000 After Instruction A FF F1EF 579B T 2345 T 2345 C 0 C 1 C16 1 C16 1 0100 AR3† 00FE 0100h 1534 0100h 1534 0101h 3456 0101h 3456 AR3 Data Memory † Because this instruction is a long-operand instruction, AR3 is decremented by 2 after the execution. SPRU179C Assembly Language Instructions 4-47 Store Accumulator in Long Word Syntax 1: 2: Operands dbl(Lmem) = src dual(Lmem) = src src: Lmem: Opcode 15 0 14 1 A (accumulator A) B (accumulator B) Long data-memory operand 13 0 12 0 11 1 10 1 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (src(31–0)) ³ Lmem Status Bits None Description This instruction stores the content of src in a 32-bit long data-memory location Lmem. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Lmem. Cycles 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem. Classes Class 13A (see page 3-30) Class 13B (see page 3-31) Example 1 dbl(*AR3+) = B Before Instruction B 00 6CAC BD90 After Instruction B 00 6CAC BD90 0100 AR3† 0102 0100h 0000 0100h 6CAC 0101h 0000 0101h BD90 AR3 Data Memory † Because this instruction is a long-operand instruction, AR3 is incremented by 2 after the execution. Example 2 dbl(*AR3–) = B Before Instruction B 00 6CAC BD90 After Instruction B 00 6CAC BD90 0101 AR3† 00FF 0100h 0000 0100h BD90 0101h 0000 0101h 6CAC AR3 Data Memory † Because this instruction is a long-operand instruction, AR3 is decremented by 2 after the execution. 4-48 Assembly Language Instructions SPRU179C Double-Precision/Dual 16-Bit Subtract From Accumulator Syntax 1: 2: Operands Opcode src = src – dbl(Lmem) src – = dbl(Lmem) src = src – dual(Lmem) src – = dual(Lmem) Lmem: src: 15 0 14 1 Long data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 0 10 1 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution If C16 = 0 Then (src) * (Lmem) ³ src Else (src(31–16)) * (Lmem(31–16)) ³ src(39–16) (src(15–0)) * (Lmem(15–0)) ³ src(15–0) Status Bits Affected by SXM and OVM (only if C16 = 0) Affects C and OVsrc Description This instruction subtracts the 32-bit long data-memory operand Lmem from the content of src, and stores the result in src. The value of C16 determines the mode of the instruction: - If C16 = 0, the instruction is executed in double-precision mode. Lmem is subtracted from the content of src. - If C16 = 1, the instruction is executed in dual 16-bit mode. The 16 MSBs of Lmem are subtracted from the high part of src (bits 31–16) and the result is stored in the high part of src (bits 39–16). At the same time, the 16 LSBs of Lmem are subtracted from the low part of src (bits15–0) and the result is stored in the low part of src (bits 15–0). Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Lmem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem. Classes SPRU179C Class 9A (see page 3-22) Class 9B (see page 3-23) Assembly Language Instructions 4-49 Double-Precision/Dual 16-Bit Subtract From Accumulator Example 1 A = A – dbl(*AR3+) Before Instruction A 00 5678 8933 C16 0 After Instruction A C16 00 4144 54DD 0 0100 AR3† 0102 0100h 1534 0100h 1534 0101h 3456 0101h 3456 AR3 Data Memory † Because this instruction is a long-operand instruction, AR3 is incremented by 2 after the execution. Example 2 A = A – dbl(*AR3–) Before Instruction A 00 5678 3933 After Instruction A 00 4144 04DD C 1 C 1 C16 1 C16 1 AR3 0100 AR3† 00FE 0100h 1534 0100h 1534 0101h 3456 0101h 3456 Data Memory † Because this instruction is a long-operand instruction, AR3 is decremented by 2 after the execution. 4-50 Assembly Language Instructions SPRU179C Long-Word Load With T Subtract/Dual 16-Bit Load With T Subtract dst = dbl(Lmem) – T dst = dual(Lmem) – T Syntax 1: 2: Operands Lmem: dst: Opcode 15 0 14 1 Long data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 1 10 1 9 0 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution If C16 = 1 Then (Lmem(31–16)) * (T) ³ dst(39–16) (Lmem(15–0)) * (T) ³ dst(15–0) Else (Lmem) * ((T) + (T << 16)) ³ dst Status Bits Affected by SXM and OVM (only if C16 = 0) Affects C and OVdst Description This instruction subtracts the content of T from the 32-bit long data-memory operand Lmem and stores the result in dst. The value of C16 determines the mode of the instruction: - If C16 = 0, the instruction is executed in double-precision mode. A 32-bit value composed of the content of T concatenated with the content of T leftshifted 16 bits (T << 16 + T) is subtracted from Lmem. The result is stored in dst. - If C16 = 1, the instruction is executed in dual 16-bit mode. The content of T is subtracted from the 16 MSBs of Lmem and the result is stored in the high part of dst (bits 39–16). At the same time, the content of T is subtracted from the 16 LSBs of Lmem and the result is stored in the low part of dst (bits 15–0). In this mode, the results are not saturated regardless of the value of the OVM bit. Note: This instruction is meaningful only if C16 is set to 1 (dual 16-bit mode). Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Lmem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Lmem. SPRU179C Assembly Language Instructions 4-51 Long-Word Load With T Subtract/Dual 16-Bit Load With T Subtract Classes Class 9A (see page 3-22) Class 9B (see page 3-23) Example 1 A = dbl(*AR3+) – T Before Instruction After Instruction A 00 0000 0000 A FF F1EF 1111 T 2345 T 2345 C16 0 AR3 0100 AR3† C16 0102 0100h 1534 0100h 1534 0101h 3456 0101h 3456 0 Data Memory † Because this instruction is a long-operand instruction, AR3 is incremented by 2 after the execution. Example 2 A = dbl(*AR3–) – T Before Instruction After Instruction A 00 0000 0000 A FF F1EF 1111 T 2345 T 2345 C16 1 AR3 0100 AR3† C16 00FE 0100h 1534 0100h 1534 0101h 3456 0101h 3456 1 Data Memory † Because this instruction is a long operand instruction, AR3 is decremented by 2 after the execution. 4-52 Assembly Language Instructions SPRU179C Accumulator Exponent Syntax T = exp(src) Operands src: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 0 8 S 7 1 6 0 5 0 4 0 3 1 2 1 1 1 0 0 Execution If (src) + 0 Then 0³T Else (Number of leading bits of src) * 8 ³ T Status Bits None Description This instruction computes the exponent value, which is a signed 2s-complement value in the –8 to 31 range, and stores the result in T. The exponent is computed by calculating the number of leading bits in src and subtracting 8 from this value. The number of leading bits is equivalent to the number of left shifts needed to eliminate the significant bits from the 40-bit src with the exception of the sign bit. The src is not modified after this instruction. The result of subtracting 8 from the number of leading bits produces a negative exponent for accumulator values that have significant bits in the guard bits (the eight MSBs of the accumulator used in error detection and correction). See the normalization instruction (page 4-124). Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 T = exp(A) Before Instruction A T Example 2 FF FFFF FFCB 0000 After Instruction A FF FFFF FFCB –53 T –53 0019 25 T = exp(B) Before Instruction After Instruction B 07 8543 2105 B 07 8543 2105 T FFFC T FFFC –4† † The value in accumulator B has significant bits in the guard bits, which results in a negative exponent. SPRU179C Assembly Language Instructions 4-53 Far Branch Unconditionally Syntax far [d]goto extpmad Operands 0 v extpmad v 7F FFFF Opcode 15 1 14 1 13 1 12 1 11 1 10 0 9 Z 8 0 7 1 6 5 4 3 2 1 0 7-bit constant = pmad(22–16) 16-bit constant = pmad(15–0) Execution (pmad(15–0)) ³ PC (pmad(22–16)) ³ XPC Status Bits None Description This instruction passes control to the program-memory address pmad (bits 15–0) on the page specified by pmad (bits 22–16). The pmad can be either a symbolic or numeric address. If the branch is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following the branch instruction is fetched from program memory and executed. Note: This instruction is not repeatable. This instruction cannot be included in a blockrepeat instruction. Words 2 words Cycles 4 cycles 2 cycles (delayed) Classes Class 29A (see page 3-68) Example 1 far goto 012000h Before Instruction PC 1000 XPC 00 After Instruction PC XPC 2000 01 2000h is loaded into the PC, 01h is loaded into XPC, and the program continues executing from that location. Example 2 far dgoto 7F1000h *AR1+ = *AR1+ & #4444h Before Instruction PC XPC 2000 00 After Instruction PC XPC 1000 7F After the operand has been ANDed with 4444h, the program continues executing from location 1000h on page 7Fh. 4-54 Assembly Language Instructions SPRU179C Far Branch to Location Specified by Accumulator Syntax far [d]goto src Operands src: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 Z 8 S 7 1 6 1 5 1 4 0 3 0 2 1 1 1 0 0 Execution (src(15–0)) ³ PC (src(22–16)) ³ XPC Status Bits None Description This instruction loads the XPC with the value in src (bits 22–16) and passes control to the 16-bit address in the low part of src (bits 15–0). If the branch is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following the branch instruction is fetched from program memory and executed. Note: This instruction is not repeatable. This instruction cannot be included in a blockrepeat instruction. Words 1 word Cycles 6 cycles 4 cycles (delayed) Classes Class 30A (see page 3-69) Example 1 far goto A Before Instruction A PC 00 0001 3000 1000 XPC 00 After Instruction A 00 0001 3000 PC 3000 XPC 01 1h is loaded into the XPC, 3000h is loaded into the PC, and the program continues executing from that location on page 1h. Example 2 far dgoto B *AR1+ = *AR1+ & #(4444h *AR1+) Before Instruction B XPC 00 007F 2000 01 After Instruction B 00 007F 2000 XPC 7F After the operand has been ANDed with 4444h value, 7Fh is loaded into the XPC, and the program continues executing from location 2000h on page 7Fh. SPRU179C Assembly Language Instructions 4-55 Far Call Subroutine at Location Specified by Accumulator Syntax far [d]call src Operands src: Opcode 15 1 Execution A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 Z 8 S 7 1 6 1 5 1 4 0 3 0 2 1 1 1 0 1 Nondelayed (SP) – 1 ³ SP (PC) + 1 ³ TOS (SP) – 1 ³ SP (XPC) ³ TOS (src(15–0)) ³ PC (src(22–16)) ³ XPC Delayed (SP) – 1 ³ SP (PC) + 3 ³ TOS (SP) – 1 ³ SP (XPC) ³ TOS (src(15–0)) ³ PC (src(22–16)) ³ XPC Status Bits None Description This instruction loads the XPC with the value in src (bits 22–16) and passes control to the 16-bit address in the low part of src (bits 15–0). If the call is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following the call instruction is fetched from program memory and executed. Note: This instruction is not repeatable. This instruction cannot be included in a blockrepeat instruction. Words 1 word Cycles 6 cycles 4 cycles (delayed) Classes Class 30B (see page 3-69) 4-56 Assembly Language Instructions SPRU179C Far Call Subroutine at Location Specified by Accumulator Example 1 far call A Before Instruction A 00 007F 3000 PC 0025 XPC 00 SP 1111 1110h 110Fh After Instruction A 00 007F 3000 PC 3000 XPC 7F SP 110F 4567 1110h 0026 4567 110Fh 0000 Data Memory Example 2 far dcall B *AR1+ = *AR1+ & #4444h Before Instruction B PC XPC 00 0020 2000 0025 7F After Instruction B 00 0020 2000 PC XPC 2000 20 SP 1111 SP 110F 1110h 4567 1110h 0028 110Fh 4567 110Fh 007F Data Memory After the memory location has been ANDed with 4444h, the program continues executing from location 2000h on page 20h. SPRU179C Assembly Language Instructions 4-57 Far Call Unconditionally Syntax far [d]call extpmad Operands 0 v extpmad v 7F FFFF Opcode 15 1 14 1 13 1 12 1 11 1 10 0 9 Z 8 1 7 1 6 5 4 3 2 1 0 7-bit constant = pmad(22–16) 16-bit constant = pmad(15-0) Execution Nondelayed (SP) * 1 ³ SP (PC) ) 2 ³ TOS (SP) – 1 ³ SP (XPC) ³ TOS (pmad(15–0)) ³ PC (pmad(22–16)) ³ XPC Delayed (SP) – 1 ³ SP (PC) + 4 ³ TOS (SP) – 1 ³ SP (XPC) ³ TOS (pmad(15–0)) ³ PC (pmad(22–16)) ³ XPC Status Bits None Description This instruction passes control to the specified program-memory address pmad (bits 15–0) on the page specified by pmad (bits 22–16). The return address is pushed onto the stack before pmad is loaded into PC. If the call is delayed (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following the call instruction is fetched from program memory and executed. Note: This instruction is not repeatable. This instruction cannot be included in a blockrepeat instruction. Words 2 words Cycles 4 cycles 2 cycles (delayed) Classes Class 29B (see page 3-68) 4-58 Assembly Language Instructions SPRU179C Far Call Unconditionally Example 1 far call 3333h Before Instruction PC 0025 XPC 00 After Instruction PC 3333 XPC 01 SP 1111 SP 110F 1110h 4567 1110h 0027 110Fh 4567 110Fh 0000 Data Memory Example 2 far dcall 1000h *AR1+ = *AR1+ & #4444h Before Instruction PC XPC 3001 7F After Instruction PC 1000 XPC 30 SP 1111 SP 110F 1110h 4567 1110h 3005 110Fh 4567 110Fh 007F Data Memory After the memory location has been ANDed with 4444h, the program continues executing from location 1000h. SPRU179C Assembly Language Instructions 4-59 Symmetrical Finite Impulse Response Filter (firs) Syntax firs(Xmem, Ymem, pmad) Operands Xmem, Ymem: Dual data-memory operands 0 v pmad v 65 535 Opcode 15 1 14 1 13 1 12 0 11 0 10 0 9 0 8 0 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y 16-bit constant Execution pmad ³ PAR While (RC) 0 0 (B) ) (A(32–16)) (Pmem addressed by PAR) ³ B ((Xmem) ) (Ymem)) << 16 ³ A (PAR) ) 1 ³ PAR (RC) * 1 ³ RC Status Bits Affected by SXM, FRCT, and OVM Affects C, OVA, and OVB Description This instruction implements a symmetrical finite impulse respone (FIR) filter. This instruction multiplies accumulator A (bits 32–16) with a Pmem value addressed by pmad (in the program address register PAR) and adds the result to the value in accumulator B. At the same time, it adds the memory operands Xmem and Ymem, shifts the result left 16 bits, and loads this value into accumulator A. In the next iteration, pmad is incremented by 1. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. Words 2 words Cycles 3 cycles Classes Class 8 (see page 3-17) Example firs(*AR3+,*AR4+,COEFFS) Before Instruction After Instruction A 00 0077 0000 A 00 00FF 0000 B 00 0000 0000 B 00 0008 762C FRCT 0 FRCT 0 AR3 0100 AR3 0101 AR4 0200 AR4 0201 0100h 0055 0100h 0055 0200h 00AA 0200h 00AA 1234 COEFFS 1234 Data Memory Program Memory COEFFS 4-60 Assembly Language Instructions SPRU179C Stack Pointer Immediate Offset Syntax SP = SP + K SP + = K Operands –128 v K v 127 Opcode 15 1 14 1 13 1 12 0 11 1 10 1 9 1 8 0 7 K 6 K 5 K 4 K 3 K 2 K 1 K 0 K Execution (SP) ) K ³ SP Status Bits None Description This instruction adds a short-immediate offset K to the SP. There is no latency for address generation in compiler mode (CPL = 1) or for stack manipulation by the instruction following this instruction. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example SP = SP + 10h Before Instruction SP SPRU179C 1000 After Instruction SP Assembly Language Instructions 1010 4-61 Far Return Syntax far [d]return Operands None Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 Z 8 0 7 1 6 1 5 1 4 0 3 0 2 1 1 0 0 0 Execution (TOS) ³ XPC (SP) ) 1 ³ SP (TOS) ³ PC (SP) ) 1 ³ SP Status Bits None Description This instruction replaces the XPC with the 7-bit value from the TOS and replaces the PC with the next 16-bit value on the stack. The SP is incremented by 1 for each of the two replacements. If the return is delayed (specified by the d prefix), the two 1-word instructions or one 2-word instruction following this instruction is fetched and executed. Note: This instruction is not repeatable. Words 1 word Cycles 6 cycles 4 cycles (delayed) Classes Class 34 (see page 3-73) Example far return Before Instruction PC XPC 2112 01 After Instruction PC XPC 1000 05 SP 0300 SP 0302 0300h 0005 0300h 0005 0301h 1000 0301h 1000 Data Memory 4-62 Assembly Language Instructions SPRU179C Enable Interrupts and Far Return From Interrupt Syntax far [d]return_enable Operands None Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 Z 8 0 7 1 6 1 5 1 4 0 3 0 2 1 1 0 0 1 Execution (TOS) ³ XPC (SP) ) 1 ³ SP (TOS) ³ PC (SP) ) 1 ³ SP 0 ³ INTM Status Bits Affects INTM Description This instruction replaces the XPC with the 7-bit value from the TOS and replaces the PC with the next 16-bit value on the stack, continuing execution from the new PC value. This instruction automatically clears the interrupt mask bit (INTM) in ST1. (Clearing this bit enables interrupts.) If the return is delayed (specified by the d prefix), the two 1-word instructions or one 2-word instruction following this instruction is fetched and executed. Note: This instruction is not repeatable. Words 1 word Cycles 6 cycles 4 cycles (delayed) Classes Class 34 (see page 3-73) Example far return_enable Before Instruction PC 2112 After Instruction PC 0110 XPC 05 XPC 6E ST1 xCxx ST1 x4xx SP 0300 SP 0302 0300h 006E 0300h 006E 0301h 0110 0301h 0110 Data Memory SPRU179C Assembly Language Instructions 4-63 Idle Until Interrupt Syntax idle(K) Operands 1vKv3 Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 N 8 N 7 1 6 1 5 1 If K is: 1 0 0 1 10 3 2 0 00 2 3 0 NN is: 1 4 0 01 Execution (PC) +1 ³ PC Status Bits Affected by INTM Description This instruction forces the program being executed to wait until an unmasked interrupt or reset occurs. The PC is incremented by 1. The device remains in an idle state (power-down mode) until it is interrupted. The idle state is exited after an unmasked interrupt, even if INTM = 1. If INTM = 1, the program continues executing at the instruction following the idle. If INTM = 0, the program branches to the corresponding interrupt service routine. The interrupt is enabled by the interrupt mask register (IMR), regardless of the INTM value. The following options, indicated by the value of K, determine the type of interrupts that can release the device from idle: K=1 Peripherals, such as the timer and the serial ports, are still active. The peripheral interrupts as well as reset and external interrupts release the processor from idle mode. K=2 Peripherals, such as the timer and the serial ports, are inactive. Reset and external interrupts release the processor from idle mode. Because interrupts are not latched in idle mode as they are in normal device operation, they must be low for a number of cycles to be acknowledged. K=3 Peripherals, such as the timer and the serial ports, are inactive and the PLL is halted. Reset and external interrupts release the processor from idle mode. Because interrupts are not latched in idle mode as they are in normal device operation, they must be low for a number of cycles to be acknowledged. Note: This instruction is not repeatable. 4-64 Assembly Language Instructions SPRU179C Idle Until Interrupt Words 1 word Cycles The number of cycles needed to execute this instruction depends on the idle period. Because the entire device is halted when K = 3, the number of cycles cannot be specified. The minimum number of cycles is 4. Classes Class 36 (see page 3-74) Example 1 idle(1) The processor idles until a reset or unmasked interrupt occurs. Example 2 idle(2) The processor idles until a reset or unmasked external interrupt occurs. Example 3 idle(3) The processor idles until a reset or unmasked external interrupt occurs. SPRU179C Assembly Language Instructions 4-65 Software Interrupt Syntax int(K) Operands 0 v K v 31 Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 1 8 1 7 1 6 1 5 0 4 K 3 K 2 K 1 K 0 K Execution (SP) * 1 ³ SP (PC) ) 1 ³ TOS interrupt vector specified by K ³ PC 1 ³ INTM Status Bits Affects INTM and IFR Description This instruction transfers program control to the interrupt vector specified by K. This instruction allows you to use your application software to execute any interrupt service routine. For a list of interrupts and their corresponding K value, see your device datasheet. During execution of the instruction, the PC is incremented by 1 and pushed onto the TOS. Then, the interrupt vector specified by K is loaded in the PC and the interrupt service routine for this interrupt is executed. The corresponding bit in the interrupt flag register (IFR) is cleared and interrupts are globally disabled (INTM = 1). The interrupt mask register (IMR) has no effect on the INTR instruction. INTR is executed regardless of the value of INTM. Note: This instruction is not repeatable. Words 1 word Cycles 3 cycles Classes Class 35 (see page 3-74) Example int (3) Before Instruction PC 0025 After Instruction PC FF8C INTM 0 INTM 1 IPTR 01FF IPTR 01FF SP 1000 SP 0FFF 0FFFh 9653 Data Memory 4-66 Assembly Language Instructions 0FFFh 0026 SPRU179C Load Accumulator With Shift Syntax dst = Smem dst = Smem << TS dst = Smem << 16 dst = Smem [ << SHIFT ] dst = Xmem [ << SHFT ] dst = #K dst = #lk [ << SHFT ] dst = #lk << 16 dst = src << ASM dst = src [ << SHIFT ] 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: For additional load instructions, see Load T/DP/ASM/ARP on page 4-71. Operands Smem: Xmem: src, dst: Single data-memory operand Dual data-memory operand A (accumulator A) B (accumulator B) 0 v K v 255 –32 768 v lk v 32 767 –16 v SHIFT v 15 0 v SHFTv 15 Opcode 1: 15 0 14 0 13 0 12 1 11 0 10 0 9 0 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 0 13 0 12 1 11 0 10 1 9 0 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 1 13 0 12 0 11 0 10 1 9 0 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 1 13 1 12 0 11 1 10 1 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 0 0 0 0 1 1 0 D 0 1 0 S H I F T 15 1 14 0 13 0 12 1 11 0 10 1 9 0 8 D 7 X 6 X 5 X 4 X 3 S 2 H 1 F 0 T 15 1 14 1 13 1 12 0 11 1 10 0 9 0 8 D 7 K 6 K 5 K 4 K 3 K 2 K 1 K 0 K 2: 3: 4: 5: 6: SPRU179C Assembly Language Instructions 4-67 Load Accumulator With Shift 7: 15 1 14 1 13 1 12 1 11 0 10 0 9 0 8 D 7 0 6 0 5 1 4 0 3 S 2 H 1 F 0 T 6 1 5 1 4 0 3 0 2 0 1 1 0 0 16-bit constant 8: 15 1 14 1 13 1 12 1 11 0 10 0 9 0 8 D 7 0 16-bit constant 9: 15 1 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 0 3 0 2 0 1 1 0 0 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 0 6 1 5 0 4 S 3 H 2 I 1 F 0 T 10: 15 1 (Smem) ³ dst (Smem) << TS ³ dst (Smem) << 16 ³ dst (Smem) << SHIFT ³ dst (Xmem) << SHFT ³ dst K ³ dst lk << SHFT ³ dst lk << 16 ³ dst (src) << ASM ³ dst (src) << SHIFT ³ dst Execution 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: Status Bits Affected by SXM in all accumulator loads Affected by OVM in loads with SHIFT or ASM shift Affects OVdst in loads with SHIFT or ASM shift Description This instruction loads dst with a data-memory value or an immediate value, supporting different shift quantities. Additionally, the instruction supports accumulator-to-accumulator moves with shift. 4-68 Assembly Language Instructions SPRU179C Load Accumulator With Shift Notes: The following syntaxes are assembled as a different syntax in certain cases. - Syntax 4: If SHIFT = 0, the instruction opcode is assembled as syntax 1. - Syntax 4: If 0 < SHIFT v 15 and Smem indirect addressing mode is in- cluded in Xmem, the instruction opcode is assembled as syntax 5. - Syntax 5: If SHFT = 0, the instruction opcode is assembled as syntax 1. - Syntax 7: If SHFT = 0 and 0 v lk v 255, the instruction opcode is assembled as syntax 6. Words Syntaxes 1, 2, 3, 5, 6, 9, and 10: 1 word Syntaxes 4, 7, and 8: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1, 2, 3, 5, 6, 9, and 10: 1 cycle Syntaxes 4, 7, and 8: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntaxes 1, 2, 3, and 5: Class 3A (see page 3-6) Syntaxes 1, 2, and 3: Class 3B (see page 3-8) Syntax 4: Class 4A (see page 3-9) Syntax 4: Class 4B (see page 3-10) Syntaxes 6, 9, and 10: Class 1 (see page 3-3) Syntaxes 7 and 8: Class 2 (see page 3-5) Example 1 A = *AR1 Before Instruction A 00 0000 0000 After Instruction A 00 0000 FEDC SXM 0 SXM 0 AR1 0200 AR1 0200 FEDC 0200h FEDC Data Memory 0200h SPRU179C Assembly Language Instructions 4-69 Load Accumulator With Shift Example 2 A = *AR1 Before Instruction A After Instruction A 00 0000 0000 FF FFFF FEDC SXM 1 SXM 1 AR1 0200 AR1 0200 FEDC 0200h FEDC Data Memory 0200h Example 3 B = *AR1 << TS Before Instruction B After Instruction B 00 0000 0000 FF FFFE DC00 SXM 1 SXM 1 AR1 0200 AR1 0200 T T 8 8 Data Memory 0200h Example 4 0200h FEDC FEDC A = *AR3+ << 16 Before Instruction A 00 0000 0000 After Instruction A FF FEDC 0000 SXM 1 SXM 1 AR3 0300 AR1 0301 FEDC 0300h FEDC Data Memory 0300h Example 5 B = #248 Before Instruction B SXM Example 6 00 0000 0000 1 After Instruction B SXM 00 0000 00F8 1 B = A << 8 Before Instruction After Instruction A 00 7FFD 0040 A 00 7FF0 0040 B 00 0000 FFFF B 7F FD00 4000 OVB 0 OVB 1 SXM 1 SXM 1 Data Memory 0200h 4-70 Assembly Language Instructions FEDC 0200h FEDC SPRU179C Load T/DP/ASM/ARP Syntax T = Smem DP = Smem DP = #k9 ASM = #k5 ARP = #k3 ASM = Smem 1: 2: 3: 4: 5: 6: For additional load instructions, see Load Accumulator With Shift on page 4-67. Operands Smem: Single data-memory operand 0 v k9 v 511 –16 v k5 v 15 0 v k3 v 7 Opcode 1: 15 0 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 1 13 0 12 0 11 0 10 1 9 1 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 1 13 1 12 0 11 1 10 0 9 1 8 K 7 K 6 K 5 K 4 K 3 K 2 K 1 K 0 K 15 1 14 1 13 1 12 0 11 1 10 1 9 0 8 1 7 0 6 0 5 0 4 K 3 K 2 K 1 K 0 K 15 1 14 1 13 1 12 1 11 0 10 1 9 0 8 0 7 1 6 0 5 1 4 0 3 0 2 K 1 K 0 K 15 0 14 0 13 1 12 1 11 0 10 0 9 1 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 2: 3: 4: 5: 6: Execution 1: (Smem) ³ T 2: (Smem(8–0)) ³ DP 3: k9 ³ DP 4: k5 ³ ASM 5: k3 ³ ARP 6: (Smem(4–0)) ³ ASM Status Bits None SPRU179C Assembly Language Instructions 4-71 Load T/DP/ASM/ARP Description This instruction loads a value into T or into the DP, ASM, and ARP fields of ST0 or ST1. The value loaded can be a single data-memory operand Smem or a constant. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1, 3, 4, 5, and 6: 1 cycle Syntax 2: 3 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntaxes 1 and 6: Class 3A (see page 3-6) Syntaxes 1 and 6: Class 3B (see page 3-8) Syntax 2: Class 5A (see page 3-11) Syntax 2: Class 5B (see page 3-11) Syntaxes 3, 4, and 5: Class 1 (see page 3-3) Example 1 T = *AR3+ Before Instruction After Instruction T 0000 T FEDC AR3 0300 AR3 0301 FEDC 0300h FEDC Data Memory 0300h Example 2 DP = *AR4 Before Instruction After Instruction AR4 0200 AR4 0200 DP 1FF DP 0DC Data Memory 0200h Example 3 FEDC 0200h DP = #23 Before Instruction DP Example 4 1FF After Instruction DP Before Instruction 00 After Instruction ASM 0F ARP = #3 Before Instruction ARP 4-72 017 ASM = @15 ASM Example 5 FEDC Assembly Language Instructions 0 After Instruction ARP 3 SPRU179C Load T/DP/ASM/ARP Example 6 ASM = @0 Before Instruction ASM DP 00 004 After Instruction ASM 1C DP 004 Data Memory 0200h SPRU179C FEDC 0200h FEDC Assembly Language Instructions 4-73 Load Memory-Mapped Register Syntax dst = MMR dst = mmr(MMR) Operands MMR: dst: Opcode 15 0 Memory-mapped register A (accumulator) B (accumulator) 14 1 13 0 12 0 11 1 10 0 9 0 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (MMR) ³ dst(15–0) 00 0000h ³ dst(39–16) Status Bits None Description This instruction loads dst with the value in memory-mapped register MMR. The nine MSBs of the effective address are cleared to 0 to designate data page 0, regardless of the current value of DP or the upper nine bits of ARx. This instruction is not affected by the value of SXM. Words 1 word Cycles 1 cycle Classes Class 3A (see page 3-6) Example 1 A = AR4 Before Instruction A AR4 Example 2 00 0000 1111 FFFF After Instruction A AR4 00 0000 FFFF FFFF B = mmr(060h) Before Instruction B 00 0000 0000 After Instruction B 00 0000 1234 Data Memory 0060h 4-74 Assembly Language Instructions 1234 0060h 1234 SPRU179C Load Accumulator With Parallel Multiply Accumulate With/Without Rounding Syntax 1: 2: 3: Operands dst = Xmem [<< 16 ] || dst_ = dst_ + T * Ymem dst = Xmem [ << 16 ] || dst_ += T * Ymem dst = Xmem [ << 16 ] || dst_ = rnd(dst_ + T * Ymem) dst: A (accumulator A) B (accumulator B) If dst = A, then dst_ = B; if dst = B, then dst_ = A Dual data-memory operands dst_: Xmem, Ymem: Opcode 15 1 14 0 13 1 12 0 11 1 10 0 9 R 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (Xmem) << 16 ³ dst (31–16) If (Rounding) Round (((Ymem) (T)) + (dst_)) ³ dst_ Else ((Ymem) (T)) + (dst_) ³ dst_ Status Bits Affected by SXM, FRCT, and OVM Affects OVdst_ Description This instruction loads the high part of dst (bits 31–16) with a 16-bit dual datamemory operand Xmem shifted left 16-bits. In parallel, this instruction multiplies a dual data-memory operand Ymem by the content of T, adds the result of the multiplication to dst_, and stores the result in dst_. If you use the rnd prefix, this instruction optionally rounds the result of the multiply and accumulate operation by adding 215 to the result and clearing the LSBs (15–0) to 0, and stores the result in dst_. Words 1 word Cycles 1 cycle Classes Class 7 (see page 3-14) SPRU179C Assembly Language Instructions 4-75 Load Accumulator With Parallel Multiply Accumulate With/Without Rounding Example 1 A = *AR4+ ||B = B + *AR5+ * T Before Instruction After Instruction A 00 0000 1000 A 00 1234 0000 B 00 0000 1111 B 00 010C 9511 T 0400 T 0400 FRCT 0 FRCT 0 AR4 0100 AR4 0101 AR5 0200 AR5 0201 0100h 1234 0100h 1234 0200h 4321 0200h 4321 Data Memory Example 2 A = *AR4+ ||B = rnd(B + *AR5+ * T) Before Instruction After Instruction A 00 0000 1000 A 00 1234 0000 B 00 0000 1111 B 00 010D 0000 T 0400 T 0400 FRCT 0 FRCT 0 AR4 0100 AR4 0101 AR5 0200 AR5 0201 0100h 1234 0100h 1234 0200h 4321 0200h 4321 Data Memory 4-76 Assembly Language Instructions SPRU179C Load Accumulator With Parallel Multiply Subtract With/Without Rounding Syntax 1: 2: 3: Operands dst = Xmem [ << 16 ] || dst_ = dst_ – T * Ymem dst = Xmem [ << 16 ] || dst_ – = T *Ymem dst = Xmem [ << 16 ] || dst_ = rnd(dst_ – T * Ymem) Xmem, Ymem: dst: Dual data-memory operands A (accumulator A) B (accumulator B) If dst = A, then dst_ = B; if dst = B, then dst_ = A dst_: Opcode 15 1 14 0 13 1 12 0 11 1 10 1 9 R 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (Xmem) << 16 ³ dst (31–16) If (Rounding) Round ((dst_) – ((T) (Ymem))) ³ dst_ Else (dst_) – ((T) (Ymem)) ³ dst_ Status Bits Affected by SXM, FRCT, and OVM Affects OVdst_ Description This instruction loads the high part of dst (bits 31–16) with a 16-bit dual datamemory operand Xmem shifted left 16 bits. In parallel, this instruction multiplies a dual data-memory operand Ymem by the content of T, subtracts the result of the multiplication from dst_, and stores the result in dst_. If you use the rnd prefix, this instruction optionally rounds the result of the multiply and subtract operation by adding 215 to the result and clearing the LSBs (15–0) to 0, and stores the result in dst_. Words 1 word Cycles 1 cycle Classes Class 7 (see page 3-14) SPRU179C Assembly Language Instructions 4-77 Load Accumulator With Parallel Multiply Subtract With/Without Rounding Example 1 A = *AR4+ ||B = B – *AR5+ * T Before Instruction After Instruction A 00 0000 1000 A 00 1234 0000 B 00 0000 1111 B FF FEF3 8D11 T 0400 T 0400 FRCT 0 FRCT 0 AR4 0100 AR4 0101 AR5 0200 AR5 0201 0100h 1234 0100h 1234 0200h 4321 0200h 4321 Data Memory Example 2 A = *AR4+ ||B = rnd(B – *AR5+ * T) Before Instruction After Instruction A 00 0000 1000 A 00 1234 0000 B 00 0000 1111 B FF FEF4 0000 T 0400 T 0400 FRCT 0 FRCT 0 AR4 0100 AR4 0101 AR5 0200 AR5 0201 0100h 1234 0100h 1234 0200h 4321 0200h 4321 Data Memory 4-78 Assembly Language Instructions SPRU179C Load Memory Value in Accumulator High With Rounding Syntax dst = rnd(Smem) Operands Smem: dst: Opcode 15 0 14 0 Single data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 0 10 1 9 1 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (Smem) << 16 ) 1 << 15 ³ dst(31–16) Status Bits Affected by SXM Description This instruction loads the data-memory value Smem shifted left 16 bits into the high part of dst (bits 31–16). Smem is rounded by adding 215 to this value and clearing the 15 LSBs (14–0) of the accumulator to 0. Bit 15 of the accumulator is set to 1. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example A = rnd(*AR1) Before Instruction A 00 0000 0000 After Instruction A 00 FEDC 8000 SXM 0 SXM 0 AR1 0200 AR1 0200 FEDC 0200h FEDC Data Memory 0200h SPRU179C Assembly Language Instructions 4-79 Load Unsigned Memory Value Syntax dst = uns(Smem) Operands Smem: dst: Opcode 15 0 14 0 Single data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 0 10 0 9 1 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (Smem) ³ dst(15–0) 00 0000h ³ dst(39–16) Status Bits None Description This instruction loads the data-memory value Smem into the low part of dst (bits 15–0). The guard bits and the high part of dst (bits 39–16) are cleared to 0. Data is then treated as an unsigned 16-bit number. There is no sign extension regardless of the status of the SXM bit. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example A = uns(*AR1) Before Instruction A AR1 00 0000 0000 After Instruction A 00 0000 FEDC 0200 AR1 0200 FEDC 0200h FEDC Data Memory 0200h 4-80 Assembly Language Instructions SPRU179C Least Mean Square (lms) Syntax lms(Xmem, Ymem) Operands Xmem, Ymem: Opcode 15 1 14 1 13 1 Dual data-memory operands 12 0 11 0 10 0 9 0 8 1 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (A) ) (Xmem) << 16 ) 215 ³ A (B) ) (Xmem) (Ymem) ³ B Status Bits Affected by SXM, FRCT, and OVM Affects C, OVA, and OVB Description This instruction executes the least mean square (LMS) algorithm. The dual data-memory operand Xmem is shifted left 16 bits and added to accumulator A. The result is rounded by adding 215 to the high part of the accumulator (bits 31–16). The result is stored in accumulator A. In parallel, Xmem and Ymem are multiplied and the result is added to accumulator B. Xmem does not overwrite T; therefore, T always contains the error value used to update coefficients. Words 1 word Cycles 1 cycle Classes Class 7 (see page 3-14) Example lms(*AR3+,*AR4+) Before Instruction A 00 7777 8888 B 00 0000 0100 FRCT 0 After Instruction A 00 77CD 0888 B 00 0000 3972 FRCT 0 AR3 0100 AR3 0101 AR4 0200 AR4 0201 0100h 0055 0100h 0055 0200h 00AA 0200h 00AA Data Memory SPRU179C Assembly Language Instructions 4-81 Load T and Insert Delay Syntax ltd(Smem) Operands Smem: Opcode 15 0 14 1 Single data-memory operand 13 0 12 0 11 1 10 1 9 0 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (Smem) ³ T (Smem) ³ Smem ) 1 Status Bits None Description This instruction copies the content of a single data-memory location Smem into T and into the address following this data-memory location. When data is copied, the content of the address location remains the same. This function is useful for implementing a Z delay in digital signal processing applications. This function also contains the memory delay instruction (page 4-41). Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 24A (see page 3-58) Class 24B (see page 3-58) Example ltd(*AR3) Before Instruction After Instruction T 0000 T 6CAC AR3 0100 AR3 0100 0100h 6CAC 0100h 6CAC 0101h xxxx 0101h 6CAC Data Memory 4-82 Assembly Language Instructions SPRU179C Multiply Accumulate (MAC) With/Without Rounding Syntax src = src + T * Smem src + = T * Smem src = rnd(src + T * Smem) dst = src + Xmem * Ymem [, T = Xmem] dst + = Xmem * Ymem [, T = Xmem] dst = rnd(src + Xmem * Ymem) [, T = Xmem] dst = src + T * #lk dst + = T * #lk dst = src + Smem * #lk [, T = Smem] dst + = Smem * #lk [, T = Smem] 1: 2: 3: 4: Operands Smem: Xmem, Ymem: src, dst: Single data-memory operands Dual data-memory operands A (accumulator A) B (accumulator B) –32 768 v lk v 32 767 Opcode 1: 15 0 14 0 13 1 12 0 11 1 10 0 9 R 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 0 13 1 12 1 11 0 10 R 9 S 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 6 1 5 1 4 0 3 0 2 1 1 1 0 1 6 A 5 A 4 A 3 A 2 A 1 A 0 A 2: 3: 16-bit constant 4: 15 0 14 1 13 1 12 0 11 0 10 1 9 S 8 D 7 I 16-bit constant Execution 1: (Smem) (T) + (src) ³ src 2: (Xmem) (Ymem) + (src) ³ dst (Xmem) ³ T 3: (T) lk + (src) ³ dst 4: (Smem) lk + (src) ³ dst (Smem) ³ T Status Bits Affected by FRCT and OVM Affects OVdst SPRU179C Assembly Language Instructions 4-83 Multiply Accumulate (MAC) With/Without Rounding Description This instruction multiplies and adds with or without rounding. The result is stored in dst or src, as specified. For syntaxes 2 and 4, the data-memory value after the instruction is stored in T. T is updated in the read phase. If you use the rnd prefix, this instruction rounds the result of the multiply and accumulate operation by adding 215 to the result and clearing the LSBs (15–0) to 0. Words Syntaxes 1 and 2: 1 word Syntaxes 3 and 4: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1 and 2: 1 cycle Syntaxes 3 and 4: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntax 1: Class 3A (see page 3-6) Syntax 1: Class 3B (see page 3-8) Syntax 2: Class 7 (see page 3-14) Syntax 3: Class 2 (see page 3-5) Syntax 4: Class 6A (see page 3-12) Syntax 4: Class 6B (see page 3-13) Example 1 A = A + *AR5+ * T Before Instruction A 00 0000 1000 T 0400 FRCT 0 AR5 After Instruction A 00 0048 E000 T 0400 FRCT 0 0100 AR5 0101 1234 0100h 1234 Data Memory 0100h Example 2 B = A + #345h * T Before Instruction After Instruction A 00 0000 1000 A 00 0000 1000 B 00 0000 0000 B 00 001A 3800 T 0400 T 0400 FRCT 4-84 Assembly Language Instructions 1 FRCT 1 SPRU179C Multiply Accumulate (MAC) With/Without Rounding Example 3 A = A + *AR5+ * #1234h , T = *AR5+ Before Instruction After Instruction A 00 0000 1000 A 00 0626 1060 T 0000 T 5678 FRCT 0 AR5 FRCT 0 0100 AR5 0101 5678 0100h 5678 Data Memory 0100h Example 4 B = A + *AR5+ * *AR6+ , T = *AR5+ Before Instruction After Instruction A 00 0000 1000 A 00 0000 1000 B 00 0000 0004 B 00 0C4C 10C0 T 0008 T 5678 FRCT 1 FRCT 1 AR5 0100 AR5 0101 AR6 0200 AR6 0201 0100h 5678 0100h 5678 0200h 1234 0200h 1234 Data Memory Example 5 A = rnd(A + *AR5+ * T) Before Instruction After Instruction A 00 0000 1000 A 00 0049 0000 T 0400 T 0400 FRCT AR5 0 FRCT 0 0100 AR5 0101 1234 0100h 1234 Data Memory 0100h SPRU179C Assembly Language Instructions 4-85 Multiply Accumulate (MAC) With/Without Rounding Example 6 B = rnd(A + *AR5+ * *AR6+) , T = *AR5+ Before Instruction After Instruction A 00 0000 1000 A 00 0000 1000 B 00 0000 0004 B 00 0C4C 0000 T 0008 T 5678 FRCT 1 FRCT 1 AR5 0100 AR5 0101 AR6 0200 AR6 0201 0100h 5678 0100h 5678 0200h 1234 0200h 1234 Data Memory 4-86 Assembly Language Instructions SPRU179C Multiply by Accumulator A and Accumulate (MACA) With/Without Rounding Syntax 1: B = B + Smem * hi(A) [, T = Smem] B + = Smem * hi(A) [, T = Smem] B = rnd(B+Smem * hi(A)) [, T = Smem] 2: dst = src + T * hi(A) dst + = T * hi(A) dst = rnd(src + T * hi(A)) Operands Smem: src, dst: Opcode 1: Single data-memory operand A (accumulator A) B (accumulator B) 15 0 14 0 13 1 12 1 11 0 10 1 9 R 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 0 3 1 2 0 1 0 0 R 2: Execution 1: (Smem) (A(32–16)) + (B) ³ B (Smem) ³ T 2: (T) (A(32–16)) + (src) ³ dst Status Bits Affected by FRCT and OVM Affects OVdst and OVB in syntax 1 Description This instruction multiplies the high part of accumulator A (bits 32–16) by a single data-memory operand Smem or by the content of T, adds the product to accumulator B (syntax 1) or to src. The result is stored in accumulator B (syntax 1) or in dst. A(32–16) is used as a 17-bit operand for the multiplier. If you use the rnd prefix, this instruction rounds the result of the multiply by accumulator A operation by adding 215 to the result and clearing the 16 LSBs of dst (bits 15–0) to 0. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Syntaxes 1 and 2: Class 3A (see page 3-6) Syntaxes 1 and 2: Class 3B (see page 3-8) Syntaxes 3 and 4: Class 1 (see page 3-3) Assembly Language Instructions 4-87 Multiply by Accumulator A and Accumulate (MACA) With/Without Rounding Example 1 B = B + *AR5+ * hi(A) , T = *AR5+ Before Instruction After Instruction A 00 1234 0000 A 00 1234 0000 B 00 0000 0000 B 00 0626 0060 T 0400 T 5678 FRCT FRCT 0 AR5 0 0100 AR5 0101 5678 0100h 5678 Data Memory 0100h Example 2 B = B + T * hi(A) Before Instruction After Instruction A 00 1234 0000 A 00 1234 0000 B 00 0002 0000 B 00 009D 4BA0 T 0444 T 0444 FRCT Example 3 FRCT 1 1 B = rnd(B + *AR5+ * hi(A)) , T = *AR5+ Before Instruction After Instruction A 00 1234 0000 A 00 1234 0000 B 00 0000 0000 B 00 0626 0000 T 0400 T 5678 FRCT 0 AR5 FRCT 0 0100 AR5 0101 5678 0100h 5678 Data Memory 0100h Example 4 B = rnd(B + T * hi(A)) Before Instruction After Instruction A 00 1234 0000 A 00 1234 0000 B 00 0002 0000 B 00 009D 0000 T 0444 T 0444 FRCT 4-88 Assembly Language Instructions 1 FRCT 1 SPRU179C Multiply by Program Memory and Accumulate With Delay (macd) Syntax macd(Smem, pmad, src) Operands Smem: src: Opcode Single data-memory operand A (accumulator A) B (accumulator B) 0 v pmad v 65 535 15 0 14 1 13 1 12 1 11 1 10 0 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution pmad ³ PAR If (RC) 0 0 Then (Smem) (Pmem addressed by PAR) ) (src) ³ src (Smem) ³ T (Smem) ³ Smem ) 1 (PAR) + 1 ³ PAR Else (Smem) (Pmem addressed by PAR) ) (src) ³ src (Smem) ³ T (Smem) ³ Smem ) 1 Status Bits Affected by FRCT and OVM Affects OVsrc Description This instruction multiplies a single data-memory value Smem by a programmemory value pmad, adds the product to src, and stores the result in src. The data-memory value Smem is copied into T and into the next address following the Smem address. When this instruction is repeated, the program-memory address (in the program address register PAR) is incremented by 1. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. This function also contains the memory delay instruction (page 4-41). Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 3 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Class 23A (see page 3-55) Class 23B (see page 3-57) Assembly Language Instructions 4-89 Multiply by Program Memory and Accumulate With Delay (macd) Example macd(*AR3–,COEFFS,A) Before Instruction After Instruction A 00 0077 0000 A 00 007D 0B44 T 0008 T 0055 FRCT 0 AR3 0100 FRCT AR3 00FF 1234 COEFFS 1234 0 Program Memory COEFFS Data Memory 0100h 4-90 0055 0100h 0055 0101h 0066 0101h 0055 Assembly Language Instructions SPRU179C Multiply by Program Memory and Accumulate (macp) Syntax macp(Smem, pmad, src) Operands Smem: src: Opcode Single data-memory operand A (accumulator A) B (accumulator B) 0 v pmad v 65 535 15 0 14 1 13 1 12 1 11 1 10 0 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution (pmad) ³ PAR If (RC) 0 0 Then (Smem) (Pmem addressed by PAR) + (src) ³ src (Smem) ³ T (PAR) + 1 ³ PAR Else (Smem) (Pmem addressed by PAR) ) (src) ³ src (Smem) ³ T Status Bits Affected by FRCT and OVM Affects OVsrc Description This instruction multiplies a single data-memory value Smem by a programmemory value pmad, adds the product to src, and stores the result in src. The data-memory value Smem is copied into T. When this instruction is repeated, the program-memory address (in the program address register PAR) is incremented by 1. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 3 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Class 22A (see page 3-52) Class 22B (see page 3-54) Assembly Language Instructions 4-91 Multiply by Program Memory and Accumulate (macp) Example macp(*AR3–,COEFFS,A) Before Instruction After Instruction A 00 0077 0000 A 00 007D 0B44 T 0008 T 0055 FRCT 0 AR3 0100 FRCT AR3 00FF 1234 COEFFS 1234 0 Program Memory COEFFS Data Memory 0100h 4-92 0055 0100h 0055 0101h 0066 0101h 0066 Assembly Language Instructions SPRU179C Multiply Signed by Unsigned and Accumulate Syntax src = src + uns(Xmem) * Ymem [, T = Xmem] src + = uns(Xmem) * Ymem [, T = Xmem] Operands Xmem, Ymem: src: Opcode 15 1 14 0 13 1 Dual data-memory operands A (accumulator A) B (accumulator B) 12 0 11 0 10 1 9 1 8 S 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y signed(Ymem) ) (src) ³ src Execution unsigned(Xmem) (Xmem) ³ T Status Bits Affected by FRCT and OVM Affects OVsrc Description This instruction multiplies an unsigned data-memory value Xmem by a signed data-memory value Ymem, adds the product to src, and stores the result in src. The 16-bit unsigned value Xmem is stored in T. T is updated with the unsigned value Xmem in the read phase. The data addressed by Xmem is fed from the D bus. The data addressed by Ymem is fed from the C bus. Words 1 word Cycles 1 cycle Classes Class 7 (see page 3-14) Example A = A + uns(*AR4+) * *AR5+ , T = *AR4+ Before Instruction After Instruction A 00 0000 1000 A 00 09A0 AA84 T 0008 T 8765 FRCT 0 FRCT 0 AR4 0100 AR4 0101 AR5 0200 AR5 0201 0100h 8765 0100h 8765 0200h 1234 0200h 1234 Data Memory SPRU179C Assembly Language Instructions 4-93 Modify Auxiliary Register (mar) Syntax mar(Smem) Operands Smem: Opcode 15 0 14 1 Single data-memory operand 13 1 12 0 11 1 10 1 9 0 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution In indirect addressing mode, the auxiliary register is modified as follows: If compatibility is on (CMPT = 1), then: If (ARx = AR0) AR(ARP) is modified ARP is unchanged Else ARx is modified x ³ ARP Else compatibility is off (CMPT = 0) ARx is modified ARP is unchanged Status Bits Affected by CMPT Affects ARP (if CMPT = 1) Description This instruction modifies the content of the selected auxiliary register (ARx) as specified by Smem. In compatibility mode (CMPT = 1), this instruction modifies the ARx content as well as the auxiliary register pointer (ARP) value. If CMPT = 0, the auxiliary register is modified but ARP is not. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 1 (see page 3-3) Class 2 (see page 3-5) Example 1 mar(*AR3+) Before Instruction CMPT After Instruction CMPT ARP 0 ARP 0 AR3 4-94 0 0100 AR3 0101 Assembly Language Instructions 0 SPRU179C Modify Auxiliary Register (mar) Example 2 mar(*AR0–) Before Instruction After Instruction CMPT CMPT 1 4 ARP 4 AR4 Example 3 1 ARP 0100 AR4 00FF mar(*AR3) Before Instruction After Instruction CMPT CMPT 1 ARP 0 ARP 3 AR0 0008 AR0 0008 AR3 Example 4 1 0100 AR3 0100 mar(*+AR3) Before Instruction After Instruction CMPT CMPT 1 ARP 0 ARP 3 AR3 Example 5 1 0100 AR3 0101 mar(*AR3–) Before Instruction After Instruction CMPT CMPT 1 0 ARP 3 AR3 SPRU179C 1 ARP 0100 AR3 00FF Assembly Language Instructions 4-95 Multiply and Subtract (MAS) With/Without Rounding Syntax src = src – T * Smem src – = T * Smem src = rnd(src – T * Smem) dst = src – Xmem * Ymem [, T = Xmem] dst – = Xmem * Ymem [, T = Xmem] dst = rnd(src – Xmem * Ymem) [, T = Xmem] 1: 2: Operands Smem: Xmem, Ymem: src, dst: Opcode Single data-memory operand Dual data-memory operands A (accumulator A) B (accumulator B) 1: 15 0 14 0 13 1 12 0 11 1 10 1 9 R 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 0 13 1 12 1 11 1 10 R 9 S 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y 2: (T) ³ src (Ymem) ³ dst Execution 1: (src) – (Smem) 2: (src) * (Xmem) (Xmem) ³ T Status Bits Affected by FRCT and OVM Affects OVdst Description This instruction multiplies an operand by the content of T or multiplies two operands, subtracts the result from src unless dst is specified, and stores the result in src or dst. Xmem is loaded into T in the read phase. If you use the rnd prefix, this instruction rounds the result of the multiply and subtract operation by adding 215 to the result and clearing bits 15–0 of the result to 0. The data addressed by Xmem is fed from DB and the data addressed by Ymem is fed from CB. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 4-96 Assembly Language Instructions SPRU179C Multiply and Subtract (MAS) With/Without Rounding Classes Syntax 1: Class 3A (see page 3-6) Syntax 1: Class 3B (see page 3-8) Syntax 2: Class 7 (see page 3-14) Example 1 A = A – *AR5+ * T Before Instruction After Instruction A 00 0000 1000 A FF FFB7 4000 T 0400 T 0400 FRCT 0 AR5 FRCT 0 0100 AR5 0101 1234 0100h 1234 Data Memory 0100h Example 2 B = A – *AR5+ * *AR6+ , T = *AR5+ Before Instruction After Instruction A 00 0000 1000 A 00 0000 1000 B 00 0000 0004 B FF F9DA 0FA0 T 0008 T 5678 FRCT 1 FRCT 1 AR5 0100 AR5 0101 AR6 0200 AR6 0201 0100h 5678 0100h 5678 0200h 1234 0200h 1234 Data Memory Example 3 A = rnd(A – *AR5+ * T) Before Instruction After Instruction A 00 0000 1000 A FF FFB7 0000 T 0400 T 0400 FRCT AR5 0 FRCT 0 0100 AR5 0101 1234 0100h 1234 Data Memory 0100h SPRU179C Assembly Language Instructions 4-97 Multiply and Subtract (MAS) With/Without Rounding Example 4 B = rnd(A – *AR5+ * *AR6+) , T = *AR5+ Before Instruction After Instruction A 00 0000 1000 A 00 0000 1000 B 00 0000 0004 B FF F9DA 0000 T 0008 T 5678 FRCT 1 FRCT 1 AR5 0100 AR5 0101 AR6 0200 AR6 0201 0100h 5678 0100h 5678 0200h 1234 0200h 1234 Data Memory 4-98 Assembly Language Instructions SPRU179C Multiply by Accumulator A and Subtract (MASA) With/Without Rounding Syntax B = B – Smem * hi(A) [, T = Smem] B – = Smem * hi(A) [, T = Smem] dst = src – T * hi(A) dst – = T * hi(A) dst = rnd(src – T * hi(A)) 1: 2: Operands Smem: src, dst: Opcode Single data-memory operand A (accumulator A) B (accumulator B) 1: 15 0 14 0 13 1 12 1 11 0 10 0 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 0 3 1 2 0 1 1 0 R 2: Execution 1: (B) * (Smem) (A(32–16)) ³ B (Smem) ³ T 2: (src) * (T) (A(32–16)) ³ dst Status Bits Affected by FRCT and OVM Affects OVdst and OVB in syntax 1 Description This instruction multiplies the high part of accumulator A (bits 32–16) by a single data-memory operand Smem or by the content of T, subtracts the result from accumulator B (syntax 1) or from src. The result is stored in accumulator B (syntax 1) or in dst. T is updated with the Smem value in the read phase. If you use the rnd prefix in syntax 2, this instruction optionally rounds the result of the multiply by accumulator A and subtract operation by adding 215 to the result and clearing bits 15–0 of the result to 0. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Syntax 1: Class 3A (see page 3-6) Syntax 1: Class 3B (see page 3-8) Syntax 2: Class 1 (see page 3-3) Assembly Language Instructions 4-99 Multiply by Accumulator A and Subtract (MASA) With/Without Rounding Example 1 B = B – *AR5+ * hi(A) , T = *AR5+ Before Instruction After Instruction A 00 1234 0000 A 00 1234 0000 B 00 0002 0000 B FF F9DB FFA0 T 0400 T 5678 FRCT FRCT 0 AR5 0 0100 AR5 0101 5678 0100h 5678 Data Memory 0100h Example 2 B = B – T * hi(A) Before Instruction After Instruction A 00 1234 0000 A 00 1234 0000 B 00 0002 0000 B FF FF66 B460 T 0444 T 0444 FRCT Example 3 1 FRCT 1 B = rnd(B – T * hi(A)) Before Instruction After Instruction A 00 1234 0000 A 00 1234 0000 B 00 0002 0000 B FF FF67 0000 T 0444 T 0444 FRCT 4-100 Assembly Language Instructions 1 FRCT 1 SPRU179C Accumulator Maximum (max) Syntax dst = max(A, B) Operands dst: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 0 8 D 7 1 6 0 5 0 4 0 3 0 2 1 1 1 0 0 Execution If (A u B) Then (A) ³ dst 0³C Else (B) ³ dst 1³C Status Bits Affects C Description This instruction compares the content of the accumulators and stores the maximum value in dst. If the maximum value is in accumulator A, the carry bit, C, is cleared to 0; otherwise, it is set to 1. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 A = max(A, B) Before Instruction After Instruction A –10 B FFCB –53 C Example 2 FFF6 1 A FFF6 –10 B FFCB –53 C 0 A = max(A, B) Before Instruction After Instruction A A 00 0000 1234 00 0000 1234 B 00 0000 1234 C SPRU179C 00 0000 0055 B 0 C 1 Assembly Language Instructions 4-101 Accumulator Minimum (min) Syntax dst = min(A, B) Operands dst: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 0 8 D 7 1 6 0 5 0 4 0 3 0 2 1 1 1 0 1 Execution If (A t B) Then (A) ³ dst 0³C Else (B) ³ dst 1³C Status Bits Affects C Description This instruction compares the content of the accumulators and stores the minimum value in dst. If the minimum value is in accumulator A, the carry bit, C, is cleared to 0; otherwise, it is set to 1. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 A = min(A, B) Before Instruction After Instruction A –53 A FFCB –53 B FFF6 –10 B FFF6 –10 C Example 2 FFCB 1 C 0 A = min(A, B) Before Instruction A B C 4-102 00 0000 1234 Assembly Language Instructions After Instruction A 00 0000 1234 00 0000 1234 B 00 0000 1234 0 C 1 SPRU179C Multiply (MPY) With/Without Rounding Syntax dst = T * Smem dst = rnd(T * Smem) dst = Xmem * Ymem [, T = Xmem] dst = Smem * #lk [, T = Smem] dst = T * #lk 1: 2: 3: 4: Operands Smem: Xmem, Ymem: dst: Single data-memory operand Dual data-memory operands A (accumulator A) B (accumulator B) –32 768 v lk v 32 767 Opcode 1: 15 0 14 0 13 1 12 0 11 0 10 0 9 R 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 0 13 1 12 0 11 0 10 1 9 0 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y 15 0 14 1 13 1 12 0 11 0 10 0 9 1 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 6 1 5 1 4 0 3 0 2 1 1 1 0 0 2: 3: 16-bit constant 4: 15 1 14 1 13 1 12 1 11 0 10 0 9 0 8 D 7 0 16-bit constant Execution 1: (T) (Smem) ³ dst 2: (Xmem) (Ymem) ³ dst (Xmem) ³ T 3: (Smem) lk ³ dst (Smem) ³ T 4: (T) lk ³ dst Status Bits Affected by FRCT and OVM Affects OVdst Description This instruction multiplies the content of T or a data-memory value by a datamemory value or an immediate value, and stores the result in dst. T is loaded with the Smem or Xmem value in the read phase. If you use the rnd prefix, this instruction optionally rounds the result of the multiply operation by adding 215 to the result and then clearing bits 15–0 to 0. SPRU179C Assembly Language Instructions 4-103 Multiply (MPY) With/Without Rounding Words Syntaxes 1 and 2: 1 word Syntaxes 3 and 4: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1 and 2: 1 cycle Syntaxes 3 and 4: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntax 1: Class 3A (see page 3-6) Syntax 1: Class 3B (see page 3-8) Syntax 2: Class 7 (see page 3-14) Syntax 3: Class 6A (see page 3-12) Syntax 3: Class 6B (see page 3-13) Syntax 4: Class 2 (see page 3-5) Example 1 A = T * @13 Before Instruction After Instruction A 00 0000 0036 A 00 0000 0054 T 0006 T 0006 FRCT DP FRCT 1 DP 008 1 008 Data Memory 040Dh Example 2 040Dh 0007 0007 B = *AR2– * *AR4+0% , T = *AR2–; Before Instruction B FRCT FF FFFF FFE0 0 After Instruction B FRCT 00 0000 0020 0 AR0 0001 AR0 0001 AR2 01FF AR2 01FE AR4 0300 AR4 0301 01FFh 0010 01FFh 0010 0300h 0002 0300h 0002 Data Memory Example 3 A = T * #0FFFEh Before Instruction A 000 0000 1234 T 2000 FRCT 4-104 Assembly Language Instructions 0 After Instruction A FF FFFF C000 T 2000 FRCT 0 SPRU179C Multiply (MPY) With/Without Rounding Example 4 B = rnd(T * @0) Before Instruction After Instruction B FF FE00 0001 B 00 0626 0000 T 1234 T 1234 FRCT DP 0 004 FRCT DP 0 004 Data Memory 0200h SPRU179C 5678 0200h Assembly Language Instructions 5678 4-105 Multiply by Accumulator A (MPYA) B = Smem * hi(A) [, T = Smem] dst = T * hi(A) Syntax 1: 2: Operands Smem: dst: Opcode 1: Single data-memory operand A (accumulator A) B (accumulator B) 15 0 14 0 13 1 12 1 11 0 10 0 9 0 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 1 13 1 12 1 11 0 10 1 9 0 8 D 7 1 6 0 5 0 4 0 3 1 2 1 1 0 0 0 2: Execution 1: (Smem) (A(32–16)) ³ B (Smem) ³ T 2: (T) (A(32–16)) ³ dst Status Bits Affected by FRCT and OVM Affects OVdst (OVB in syntax 1) Description This instruction multiplies the high part of accumulator A (bits 32–16) by a single data-memory operand Smem or by the content of T, and stores the result in dst or accumulator B. T is updated in the read phase. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntax 1: Class 3A (see page 3-6) Syntax 1: Class 3B (see page 3-8) Syntax 2: Class 1 (see page 3-3) Example 1 B = *AR2 * hi(A) , T = *AR2 Before Instruction After Instruction A FF 8765 1111 A FF 8765 1111 B 00 0000 0320 B FF D743 6558 T 1234 T 5678 FRCT AR2 0 FRCT 0 0200 AR2 0200 5678 0200h 5678 Data Memory 0200h 4-106 Assembly Language Instructions SPRU179C Multiply by Accumulator A (MPYA) Example 2 B = T * hi(A) Before Instruction After Instruction A FF 8765 1111 A FF 8765 1111 B 00 0000 0320 B FF DF4D B2A3 T 4567 T 4567 FRCT SPRU179C 0 FRCT Assembly Language Instructions 0 4-107 Multiply Unsigned (MPYU) Syntax dst = T * uns(Smem) Operands Smem: dst: Opcode 15 0 14 0 Single data-memory operand A (accumulator A) B (accumulator B) 13 1 12 0 11 0 10 1 9 0 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A unsigned(Smem) ³ dst Execution unsigned(T) Status Bits Affected by FRCT and OVM Affects OVdst Description This instruction multiplies the unsigned content of T by the unsigned content of the single data-memory operand Smem, and stores the result in dst. The multiplier acts as a signed 17 17-bit multiplier for this instruction with the MSB of both operands cleared to 0. This instruction is particularly useful for computing multiple-precision products, such as multiplying two 32-bit numbers to yield a 64-bit product. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example A = T * uns(*AR0–) Before Instruction After Instruction A FF 8000 0000 A 00 3F80 0000 T 4000 T 4000 FRCT AR0 0 FRCT 0 1000 AR0 0FFF FE00 1000h FE00 Data Memory 1000h 4-108 Assembly Language Instructions SPRU179C Move Data From Data Memory to Data Memory With X, Y Addressing Syntax Ymem = Xmem Operands Xmem, Ymem: Opcode 15 1 14 1 13 1 Dual data-memory operands 12 0 11 0 10 1 9 0 8 1 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (Xmem) ³ Ymem Status Bits None Description This instruction copies the content of the data-memory location addressed by Xmem to the data-memory location addressed by Ymem. Words 1 word Cycles 1 cycle Classes Class 14 (see page 3-32) Example *AR5+ = *AR3+ Before Instruction After Instruction AR3 8000 AR3 8001 AR5 0200 AR5 0201 0200h ABCD 0200h 1234 8000h 1234 8000h 1234 Data Memory SPRU179C Assembly Language Instructions 4-109 Move Data From Data Memory to Data Memory With Destination Addressing Syntax data(dmad) = Smem Operands Smem: Single data-memory operand 0 v dmad v 65 535 Opcode 15 0 14 1 13 1 12 1 11 0 10 0 9 0 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution (dmad) ³ EAR If (RC) 0 0 Then (Smem) ³ Dmem addressed by EAR (EAR) + 1 ³ EAR Else (Smem) ³ Dmem addressed by EAR Status Bits None Description This instruction copies the content of a single data-memory operand Smem to a data-memory location addressed by a 16-bit immediate value dmad (address is in the EAB address register EAR). You can use this instruction with the single-repeat instruction to move consecutive words in data memory (using indirect addressing). The number of words to be moved is one greater than the number contained in the repeat counter at the beginning of the instruction. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 19A (see page 3-42) Class 19B (see page 3-44) Example 1 data(8000h) = @10 Before Instruction DP 004 After Instruction DP 004 Data Memory 020Ah 4-110 1234 020Ah 1234 8000h ABCD 8000h 1234 Assembly Language Instructions SPRU179C Move Data From Data Memory to Data Memory With Destination Addressing Example 2 data(1000h) = *AR3– Before Instruction AR3 01FF After Instruction AR3 01FE Data Memory 1000h SPRU179C ABCD 1000h 1234 01FFh 1234 01FFh 1234 Assembly Language Instructions 4-111 Move Data From Data Memory to Memory-Mapped Register MMR = data(dmad) mmr(MMR) = data(dmad) Syntax 1: 2: Operands MMR: Memory-mapped register 0 v dmad v 65 535 Opcode 15 0 14 1 13 1 12 1 11 0 10 0 9 1 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution dmad ³ DAR If (RC) 0 0 Then (Dmem addressed by DAR) ³ MMR (DAR) + 1 ³ DAR Else (Dmem addressed by DAR) ³ MMR Status Bits None Description This instruction copies data from a data-memory location dmad (address is in the DAB address register DAR) to a memory-mapped register MMR. The datamemory value is addressed with a 16-bit immediate value. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. Words 2 words Cycles 2 cycles Classes Class 19A (see page 3-42) Example BK = data(300h) Before Instruction After Instruction BK ABCD BK 1234 0300h 1234 0300h 1234 Data Memory 4-112 Assembly Language Instructions SPRU179C Move Data From Data Memory to Program Memory Syntax prog(pmad) = Smem Operands Smem: Single data-memory operand 0 v pmad v 65 535 Opcode 15 0 14 1 13 1 12 1 11 1 10 1 9 0 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution pmad ³ PAR If (RC) 0 0 Then (Smem) ³ Pmem addressed by PAR (PAR) + 1 ³ PAR Else (Smem) ³ Pmem addressed by PAR Status Bits None Description This instruction copies a 16-bit single data-memory operand Smem to a program-memory location addressed by a 16-bit immediate value pmad. You can use this instruction with the repeat instruction to move consecutive words in data memory (using indirect addressing) to the contiguous programmemory space addressed by 16-bit immediate values. The source and destination blocks do not have to be entirely on-chip or off-chip. When used with repeat, this instruction becomes a single-cycle instruction after the repeat pipeline starts. In addition, when repeat is used with this instruction, interrupts are inhibited. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 4 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Class 20A (see page 3-46) Class 20B (see page 3-48) Assembly Language Instructions 4-113 Move Data From Data Memory to Program Memory Example prog(0FE00h) = @0 Before Instruction DP 004 After Instruction DP 004 Data Memory 0200h 0123 0200h 0123 FFFF FE00h 0123 Program Memory FE00h 4-114 Assembly Language Instructions SPRU179C Move Data From Data Memory to Data Memory With Source Addressing Syntax Smem = data(dmad) Operands Smem: Single data-memory operand 0 v dmad v 65 535 Opcode 15 0 14 1 13 1 12 1 11 0 10 0 9 0 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution dmad ³ DAR If (RC) 0 0 Then (Dmem addressed by DAR) ³ Smem (DAR) + 1 ³ DAR Else (Dmem addressed by DAR) ³ Smem Status Bits None Description This instruction moves data from data memory to data memory. The source data-memory value is addressed with a 16-bit immediate operand dmad and is moved to Smem. You can use this instruction with the single repeat instruction to move consecutive words in data memory (using indirect addressing). The number of words to move is one greater than the number contained in the repeat counter at the beginning of the instruction. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 19A (see page 3-42) Class 19B (see page 3-44) Example 1 @0 = data(300h) Before Instruction DP 004 After Instruction DP 004 Data Memory 0200h SPRU179C ABCD 0200h 1234 0300h 1234 0300h 1234 Assembly Language Instructions 4-115 Move Data From Data Memory to Data Memory With Source Addressing Example 2 *+AR5 = data(1000h) Before Instruction AR5 After Instruction 01FF AR5 0200 1000h 1234 1000h 1234 0200h ABCD 0200h 1234 Data Memory 4-116 Assembly Language Instructions SPRU179C Move Data From Memory-Mapped Register to Data Memory data(dmad) = MMR data(dmad) = mmr(MMR) Syntax 1: 2: Operands MMR: Memory-mapped register 0 v dmad v 65 535 Opcode 15 0 14 1 13 1 12 1 11 0 10 0 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution dmad ³ EAR If (RC) 0 0 Then (MMR) ³ Dmem addressed by EAR (EAR) + 1 ³ EAR Else (MMR) ³ Dmem addressed by EAR Status Bits None Description This instruction moves data from a memory-mapped register MMR to data memory. The data-memory destination is addressed with a 16-bit immediate value dmad. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. Words 2 words Cycles 2 cycles Classes Class 19A (see page 3-42) Example data(8000h) = AR7 Before Instruction AR7 After Instruction 1234 AR7 1234 ABCD 8000h 1234 Data Memory 8000h SPRU179C Assembly Language Instructions 4-117 Move Data From Memory-Mapped Register to Memory-Mapped Register MMRy = MMRx mmr(MMRy) = mmr(MMRx) Syntax 1: 2: Operands MMRx: MMRy: Opcode 15 1 14 1 AR0–AR7, SP AR0–AR7, SP 13 1 12 0 Register 11 0 10 1 9 1 MMRX/MMRY 8 1 7 M 6 M 5 R 4 X Register 3 M 2 M 1 R 0 Y MMRX/MMRY AR0 0000 AR5 0101 AR1 0001 AR6 0110 AR2 0010 AR7 0111 AR3 0011 SP 1000 AR4 0100 Execution (MMRx) ³ MMRy Status Bits None Description This instruction moves the content of memory-mapped register MMRx to the memory-mapped register MMRy. Only nine operands are allowed: AR0–AR7 and SP. The read operation from MMRx is executed in the decode phase. The write operation to MMRy is executed in the access phase. Note: This instruction is not repeatable. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example AR1 = SP Before Instruction After Instruction AR1 AR1 0200 SP 4-118 3EFF 0200 SP 0200 Assembly Language Instructions SPRU179C Move Data From Program Memory to Data Memory Syntax Smem = prog(pmad) Operands Smem: Single data-memory operand 0 v pmad v 65 535 Opcode 15 0 14 1 13 1 12 1 11 1 10 1 9 0 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution pmad ³ PAR If (RC) 0 0 Then (Pmem addressed by PAR) ³ Smem (PAR) + 1 ³ PAR Else (Pmem addressed by PAR) ³ Smem Status Bits None Description This instruction moves a word in program memory addressed by a 16-bit immediate value pmad to a data-memory location addressed by Smem. This instruction can be used with the repeat instruction to move consecutive words addressed by a 16-bit immediate program address to contiguous datamemory locations addressed by Smem. The source and destination blocks do not have to be entirely on-chip or off-chip. When used with repeat, this instruction becomes a single-cycle instruction after the repeat pipeline starts. In addition, when repeat is used with this instruction, interrupts are inhibited. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 3 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Class 21A (see page 3-49) Class 21B (see page 3-51) Assembly Language Instructions 4-119 Move Data From Program Memory to Data Memory Example 1 @5 = prog(0FE00h) Before Instruction DP 006 After Instruction DP 006 Program Memory FE00h 8A55 FE00h 8A55 FFFF 0305h 8A55 Data Memory 0305h Example 2 *AR7–0 = prog(2000h) Before Instruction After Instruction AR0 0002 AR0 0002 AR7 0FFE AR7 0FFC 1234 2000h 1234 Program Memory 2000h Data Memory 0FFEh 4-120 Assembly Language Instructions ABCD 0FFEh 1234 SPRU179C Negate Accumulator Syntax dst = –src Operands src, dst: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 0 3 0 2 1 1 0 0 0 –1 ³ dst Execution (src) Status Bits Affected by OVM Affects C and OVdst Description This instruction computes the 2s complement of the content of src (either A or B) and stores the result in dst. This instruction clears the carry bit, C, to 0 for all nonzero values of the accumulator. If the accumulator equals 0, the carry bit is set to 1. If the accumulator equals FF 8000 0000h, the negate operation causes an overflow because the 2s complement of FF 8000 0000h exceeds the lower 32 bits of the accumulator. If OVM = 1, dst is assigned 00 7FFF FFFFh. If OVM = 0, dst is assigned 00 8000 0000h. The OV bit for dst is set to indicate overflow in either case. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 B = –A Before Instruction After Instruction A FF FFFF F228 A FF FFFF F228 B 00 0000 1234 B 00 0000 0DD8 OVA Example 2 0 OVA 0 A = –B Before Instruction After Instruction A 00 0000 1234 A FF 8000 0000 B 00 8000 0000 B 00 8000 0000 OVB Example 3 0 OVB 0 A = –A Before Instruction A 80 0000 0000 After Instruction A 80 0000 0000 OVA SPRU179C 0 OVA 1 OVM 0 OVM 0 Assembly Language Instructions 4-121 Negate Accumulator Example 4 A = –A Before Instruction A 80 0000 0000 After Instruction A 00 7FFF FFFF OVA OVA 1 OVM 4-122 0 1 OVM 1 Assembly Language Instructions SPRU179C No Operation (nop) Syntax nop Operands None Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 0 8 0 7 1 6 0 5 0 4 1 3 0 2 1 1 0 0 1 Execution None Status Bits None Description No operation is performed. Only the PC is incremented. This is useful to create pipeline and execution delays. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example nop No operation is performed. SPRU179C Assembly Language Instructions 4-123 Normalization dst = src << TS dst = norm(src, TS) Syntax 1: 2: Operands src, dst : Opcode 15 1 14 1 A (accumulator A) B (accumulator B) 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 0 3 1 2 1 1 1 0 1 Execution (src) << TS ³ dst Status Bits Affected by SXM and OVM Affects OVdst Description The signed number contained in src is normalized and the value is stored in dst. Normalizing a fixed-point number separates the number into a mantissa and an exponent by finding the magnitude of the sign-extended number. This instruction allows single-cycle normalization of the accumulator once the accumulator exponent instruction, which computes the exponent of a number, has executed. The shift value is defined by T(5–0) and coded as a 2s-complement number. The valid shift values are –16 to 31. For the normalization, the shifter needs the shift value (in T) in the read phase; the normalization is executed in the execution phase. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 A = A << TS Before Instruction After Instruction A A FF 8008 0000 T Example 2 FF FFFF F001 0013 T 0013 A = B << TS Before Instruction After Instruction A A 00 4214 1414 B 21 0A0A 0A0A B 21 0A0A 0A0A T 4-124 FF FFFF F001 0FF9 T 0FF9 Assembly Language Instructions SPRU179C OR With Accumulator Syntax src = src | Smem src |= Smem dst = src | #lk [ << SHFT ] dst |= #lk [ << SHFT ] dst = src | #lk << 16 dst |= #lk << 16 dst = dst | src [ << SHIFT ] dst |= src [ << SHIFT ] 1: 2: 3: 4: Operands src, dst : A (accumulator A) B (accumulator B) Smem : Single data-memory operand 0 v SHFT v 15 –16 v SHIFT v 15 0 v lk v 65 535 Opcode 1: 15 0 14 0 13 0 12 1 11 1 10 0 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 6 1 5 0 4 0 3 S 2 H 1 F 0 T 6 1 5 1 4 0 3 0 2 1 1 0 0 0 6 0 5 1 4 S 3 H 2 I 1 F 0 T 2: 16-bit constant 3: 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 16-bit constant 4: 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 1 Execution 1: (Smem) OR (src(15–0)) ³ src src(39–16) unchanged 2: lk << SHFT OR (src) ³ dst 3: lk << 16 OR (src) ³ dst 4: (src or [dst]) OR (src) << SHIFT ³ dst Status Bits None Description This instruction ORs the src with a single data-memory operand Smem, a leftshifted 16-bit immediate value lk, dst, or with itself. The result is stored in dst, or src if dst is not specified. The values can be shifted as indicated by the instruction. For a positive (left) shift, low-order bits are cleared and high-order bits are not sign extended. For a negative (right) shift, high-order bits are not sign extended. SPRU179C Assembly Language Instructions 4-125 OR With Accumulator Words Syntaxes 1 and 4: 1 word Syntaxes 2 and 3: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1 and 4: 1 cycle Syntaxes 2 and 3: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntax 1: Class 3A (see page 3-6) Syntax 1: Class 3B (see page 3-8) Syntaxes 2 and 3: Class 2 (see page 3-5) Syntax 4: Class 1 (see page 3-3) Example 1 A = *AR3+ | A Before Instruction A AR3 00 00FF 1200 After Instruction A 00 00FF 1700 0100 AR3 0101 1500 0100h 1500 Data Memory 0100h Example 2 B = B | A << +3 Before Instruction After Instruction A A 00 0000 1200 B 4-126 00 0000 1200 00 0000 1800 B 00 0000 9800 Assembly Language Instructions SPRU179C OR Memory With Constant Syntax Smem = Smem | #lk Smem |= #lk Operands Smem: Single data-memory operand 0 v lk v 65 535 Opcode 15 0 14 1 13 1 12 0 11 1 10 0 9 0 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution lk OR (Smem) ³ Smem Status Bits None Description This instruction ORs the single data-memory operand Smem with a 16-bit constant lk, and stores the result in Smem. This instruction is a memory-tomemory operation. Note: This instruction is not repeatable. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 18A (see page 3-41) Class 18B (see page 3-41) Example *AR4+ = *AR4+ | #0404h Before Instruction AR4 After Instruction 0100 AR4 0101 4444 0100h 4444 Data Memory 0100h SPRU179C Assembly Language Instructions 4-127 Polynominal Evaluation (poly) Syntax poly(Smem) Operands Smem : Opcode 15 0 14 0 Single data-memory operand 13 1 12 1 11 0 10 1 9 1 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution Round (A(32–16) (T) ) (B)) ³ A (Smem) << 16 ³ B Status Bits Affected by FRCT, OVM, and SXM Affects OVA Description This instruction shifts the content of the single data-memory operand Smem 16 bits to the left and stores the result in accumulator B. In parallel, this instruction multiplies the high part of accumulator A (bits 32–16) by the content of T, adds the product to accumulator B, rounds the result of this operation, and stores the final result in accumulator A. This instruction is useful for polynomial evaluation to implement computations that take one cycle per monomial to execute. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example poly(*AR3+%) Before Instruction After Instruction A 00 1234 0000 A 00 0627 0000 B 00 0001 0000 B 00 2000 0000 T 5678 T 5678 AR3 0200 AR3 0201 2000 0200h 2000 Data Memory 0200h 4-128 Assembly Language Instructions SPRU179C Pop Top of Stack to Data Memory Syntax Smem = pop() Operands Smem: Opcode 15 1 14 0 Single data-memory operand 13 0 12 0 11 1 10 0 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (TOS) ³ Smem (SP) ) 1 ³ SP Status Bits None Description This instruction moves the content of the data-memory location addressed by SP to the memory location specified by Smem. SP is incremented by 1. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 17A (see page 3-38) Class 17B (see page 3-40) Example @10 = pop() Before Instruction After Instruction DP 008 DP 008 SP 0300 SP 0301 0300h 0092 0300h 0092 040Ah 0055 040Ah 0092 Data Memory SPRU179C Assembly Language Instructions 4-129 Pop Top of Stack to Memory-Mapped Register MMR = pop() mmr(MMR) = pop() Syntax 1: 2: Operands MMR: Opcode 15 1 Memory-mapped register 14 0 13 0 12 0 11 1 10 0 9 1 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (TOS) ³ MMR (SP) ) 1 ³ SP Status Bits None Description This instruction moves the content of the data-memory location addressed by SP to the specified memory-mapped register MMR. SP is incremented by 1. Words 1 word Cycles 1 cycle Classes Class 17A (see page 3-38) Example AR5 = pop() Before Instruction After Instruction AR5 0055 AR5 0060 SP 03F0 SP 03F1 03F0h 0060 03F0h 0060 Data Memory 4-130 Assembly Language Instructions SPRU179C Read Data From Port Syntax Smem = port(PA) Operands Smem: Single data-memory operand 0 v PA v 65 535 Opcode 15 0 14 1 13 1 12 1 11 0 10 1 9 0 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Port address Execution (PA) ³ Smem Status Bits None Description This instruction reads a 16-bit value from an external I/O port PA (16-bit immediate address) into the specified data-memory location Smem. The IS signal goes low to indicate an I/O access, and the IOSTRB and READY timings are the same as for an external data memory read. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles (dependent on the external I/O operation) Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 27A (see page 3-65) Class 27B (see page 3-65) Example @INDAT = port(05) ; INDAT .equ 60h Before Instruction DP 000 After Instruction DP 000 I/O Memory 0005h 7FFA 0005h 7FFA 0000 0060h 7FFA Data Memory 0060h SPRU179C Assembly Language Instructions 4-131 Write Data to Port Syntax port(PA) = Smem Operands Smem: Single data-memory operand 0 v PA v 65 535 Opcode 15 0 14 1 13 1 12 1 11 0 10 1 9 0 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Port address Execution (Smem) ³ PA Status Bits None Description This instruction writes a 16-bit value from the specified data-memory location Smem to an external I/O port PA. The IS signal goes low to indicate an I/O access, and the IOSTRB and READY timings are the same as for an external data memory read. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles (dependent on the external I/O operation) Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 28A (see page 3-66) Class 28B (see page 3-67) Example port(7h) = @OUTDAT ; OUTDAT .equ 07h Before Instruction DP 001 After Instruction DP 001 I/O Memory 0005h 0000 0005h 7FFA 7FFA 0087h 7FFA Data Memory 0087h 4-132 Assembly Language Instructions SPRU179C Push Data-Memory Value Onto Stack Syntax push(Smem) Operands Smem: Opcode 15 0 14 1 Single data-memory operand 13 0 12 0 11 1 10 0 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (SP) * 1 ³ SP (Smem) ³ TOS Status Bits None Description After SP has been decremented by 1, this instruction stores the content of the memory location Smem in the data-memory location addressed by SP. SP is read during the decode phase; it is stored during the access phase. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 16A (see page 3-35) Class 16B (see page 3-37) Example push(*AR3+) Before Instruction After Instruction AR3 0200 AR3 0201 SP 8000 SP 7FFF 0200h 07FF 0200h 07FF 7FFFh 0092 7FFFh 07FF Data Memory SPRU179C Assembly Language Instructions 4-133 Push Memory-Mapped Register Onto Stack push(MMR) push(mmr(MMR)) Syntax 1: 2: Operands MMR: Opcode 15 0 Memory-mapped register 14 1 13 0 12 0 11 1 10 0 9 1 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (SP) * 1 ³ SP (MMR) ³ TOS Status Bits None Description After SP has been decremented by 1, this instruction stores the content of the memory-mapped register MMR in the data-memory location addressed by SP. Words 1 word Cycles 1 cycle Classes Class 16A (see page 3-35) Example push(BRC) Before Instruction After Instruction BRC 1234 BRC 1234 SP 2000 SP 1FFF 1FFFh 07FF 1FFFh 1234 Data Memory 4-134 Assembly Language Instructions SPRU179C Return Conditionally Syntax if (cond [, cond [, cond ] ] ) [d]return Operands The following table lists the conditions (cond operand) for this instruction. Cond Condition Code Cond Description Condition Code BIO BIO low 0000 0011 NBIO BIO high 0000 0010 C C=1 0000 1100 NC C=0 0000 1000 TC TC = 1 0011 0000 NTC TC = 0 0010 0000 AEQ (A) = 0 0100 0101 BEQ (B) = 0 0100 1101 ANEQ (A) 0 0 0100 0100 BNEQ (B) 0 0 0100 1100 AGT (A) u 0 0100 0110 BGT (B) u 0 0100 1110 AGEQ (A) w 0 0100 0010 BGEQ (B) w 0 0100 1010 ALT (A) t 0 0100 0011 BLT (B) t 0 0100 1011 ALEQ (A) v 0 0100 0111 BLEQ (B) v 0 0100 1111 AOV A overflow 0111 0000 BOV B overflow 0111 1000 ANOV A no overflow 0110 0000 BNOV B no overflow 0110 1000 UNC Opcode Description Unconditional 0000 0000 15 1 14 1 13 1 12 1 11 1 10 1 9 Z 8 0 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C Execution If (cond(s)) Then (TOS) ³ PC (SP) + 1 ³ SP Else (PC) + 1 ³ PC Status Bits None Description If the conditions given by cond are met, this instruction replaces the PC with the data-memory value from the TOS and increments the SP by 1. If the conditions are not met, this instruction just increments the PC by 1. If the return is delayed (specified by the d prefix), the two 1-word instructions or one 2-word instruction following this instruction is fetched and executed. The two instruction words following this instruction have no effect on the condition(s) being tested. SPRU179C Assembly Language Instructions 4-135 Return Conditionally This instruction tests multiple conditions before passing control to another section of the program. It can test the conditions individually or in combination with other conditions. You can combine conditions from only one group as follows: Group 1 You can select up to two conditions. Each of these conditions must be from a different category (category A or B); you cannot have two conditions from the same category. For example, you can test EQ and OV at the same time but you cannot test GT and NEQ at the same time. The accumulator must be the same for both conditions; you cannot test conditions for both accumulators with the same instruction. For example, you can test AGT and AOV at the same time, but you cannot test AGT and BOV at the same time. Group 2 You can select up to three conditions. Each of these conditions must be from a different category (category A, B, or C); you cannot have two conditions from the same category. For example, you can test TC, C, and BIO at the same time but you cannot test NTC, C, and NC at the same time. Conditions for This Instruction Group 2 Group 1 Category A Category B Category A Category B Category C EQ OV TC C BIO NEQ NOV NTC NC NBIO LT LEQ GT GEQ Note: This instruction is not repeatable. Words 1 word Cycles 5 cycles (true condition) 3 cycles (false condition) 3 cycles (delayed) Classes Class 32 (see page 3-72) 4-136 Assembly Language Instructions SPRU179C Return Conditionally Example if (AGEQ, ANOV) return ; return is executed if the accumulator A ; contents are positive and the OVA bit ; is a zero Before Instruction PC OVA 0807 0 After Instruction PC OVA 2002 0 SP 0308 SP 0309 0308h 2002 0308h 2002 Data Memory SPRU179C Assembly Language Instructions 4-137 Read Program Memory Addressed by Accumulator A and Store in Data Memory Syntax Smem = prog(A) Operands Smem: Opcode 15 0 14 1 Single data-memory operand 13 1 12 1 11 1 10 1 9 1 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution A ³ PAR If ((RC)00) (Pmem (addressed by PAR)) ³ Smem (PAR) + 1 ³ PAR (RC) – 1 ³ RC Else (Pmem (addressed by PAR)) ³ Smem Status Bits None Description This instruction transfers a word from a program-memory location specified by accumulator A to a data-memory location specififed by Smem. Once the repeat pipeline is started, the instruction becomes a single-cycle instruction. The program-memory location is defined by Accumulator A, depending on the specific device, as follows: C541–C546 Devices with Extended Program Memory A(15–0) A(22–0) This instruction can be used with the repeat instruction to move consecutive words (starting with the address specified in accumulator A) to a contiguous data-memory space addressed using indirect addressing. Source and destination blocks do not need to be entirely on-chip or off-chip. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 5 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes 4-138 Class 25A (see page 3-59) Class 25B (see page 3-61) Assembly Language Instructions SPRU179C Read Program Memory Addressed by Accumulator A and Store in Data Memory Example @6 = prog(A) Before Instruction A DP 00 0000 0023 004 After Instruction A 00 0000 0023 DP 004 Program Memory 0023h 0306 0023h 0306 0075 0206h 0306 Data Memory 0206h SPRU179C Assembly Language Instructions 4-139 Software Reset Syntax reset Operands None Opcode 15 1 Execution 14 1 13 1 12 1 11 0 10 1 9 1 8 1 7 1 6 1 5 1 4 0 3 0 2 0 1 0 0 0 These fields of PMST, ST0, and ST1 are loaded with the values shown: (IPTR) << 7 ³ PC 0 ³ OVA 0 ³ OVB 1³C 1 ³ TC 0 ³ ARP 0 ³ DP 1 ³ SXM 0 ³ ASM 0 ³ BRAF 0 ³ HM 1 ³ XF 0 ³ C16 0 ³ FRCT 0 ³ CMPT 0 ³ CPL 1 ³ INTM 0 ³ IFR 0 ³ OVM Status Bits The status bits affected are listed in the execution section. Description This instruction performs a nonmaskable software reset that can be used at any time to put the C54x™ DSP into a known state. When the reset instruction is executed, the operations listed in the execution section occur. The MP/MC pin is not sampled during this software reset. The initialization of IPTR and the peripheral registers is different from the initialization using RS. This instruction is not affected by INTM; however, it sets INTM to 1 to disable interrupts. Note: This instruction is not repeatable. Words 1 word Cycles 3 cycles Classes Class 35 (see page 3-74) Example reset Before Instruction PC 0025 After Instruction PC 0080 INTM 4-140 0 INTM 1 IPTR 1 IPTR 1 Assembly Language Instructions SPRU179C Return Syntax [d]return Operands None Opcode 15 1 14 1 13 1 12 1 11 1 10 1 9 Z 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Execution (TOS) ³ PC (SP) ) 1 ³ SP Status Bits None Description This instruction replaces the value in the PC with the 16-bit value from the TOS. The SP is incremented by 1. If the return is delayed (specified by the d prefix), the two 1-word instructions or one 2-word instruction following this instruction is fetched and executed. Note: This instruction is not repeatable. Words 1 word Cycles 5 cycles 3 cycles (delayed) Classes Class 32 (see page 3-72) Example return Before Instruction After Instruction PC 2112 PC 1000 SP 0300 SP 0301 0300h 1000 0300h 1000 Data Memory SPRU179C Assembly Language Instructions 4-141 Enable Interrupts and Return From Interrupt Syntax [d]return_enable Operands None Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 Z 8 0 7 1 6 1 5 1 4 0 3 1 2 0 1 1 0 1 Execution (TOS) ³ PC (SP) ) 1 ³ SP 0 ³ INTM Status Bits Affects INTM Description This instruction replaces the value in the PC with the 16-bit value from the TOS. Execution continues from this address. The SP is incremented by 1. This instruction automatically clears the interrupt mask bit (INTM) in ST1. (Clearing this bit enables interrupts.) If the return is delayed (specified by the d prefix), the two 1-word instructions or one 2-word instruction following this instruction is fetched and executed. Note: This instruction is not repeatable. Words 1 word Cycles 5 cycles 3 cycles (delayed) Classes Class 32 (see page 3-72) Example return_enable Before Instruction PC 01C3 After Instruction PC 0110 SP 2001 SP 2002 ST1 xCxx ST1 x4xx 0110 2001h 0110 Data Memory 2001h 4-142 Assembly Language Instructions SPRU179C Enable Interrupts and Fast Return From Interrupt Syntax [d]return_fast Operands None Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 Z 8 0 7 1 6 0 5 0 4 1 3 1 2 0 1 1 0 1 Execution (RTN) ³ PC (SP) ) 1 ³ SP 0 ³ INTM Status Bits Affects INTM Description This instruction replaces the value in the PC with the 16-bit value in RTN. RTN holds the address to which the interrupt service routine should return. RTN is loaded into the PC during the return instead of reading the PC from the stack. The SP is incremented by 1. This instruction automatically clears the interrupt mask bit (INTM) in ST1. (Clearing this bit enables interrupts.) If the return is delayed (specified by the d prefix), the two 1-word instructions or one 2-word instruction following this instruction is fetched and executed. Note: You can use this instruction only if no call is performed during the interrupt service routine and no other interrupt routine is taken. This instruction is not repeatable. Words 1 word Cycles 3 cycles 1 cycle (delayed) Classes Class 33 (see page 3-73) Example return_fast Before Instruction After Instruction PC 01C3 PC 0110 SP 2001 SP 2002 ST1 xCxx ST1 x4xx 0110 2001h 0110 Data Memory 2001h SPRU179C Assembly Language Instructions 4-143 Round Accumulator Syntax dst = rnd(src) Operands src , dst: Opcode 15 1 14 1 A (accumulator A) B (accumulator B) 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 1 3 1 2 1 1 1 0 1 Execution (src) + 8000h ³ dst Status Bits Affected by OVM Description This instruction rounds the content of src (either A or B) by adding 215. The rounded value is stored in dst . Note: This instruction is not repeatable. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 B = rnd(A) Before Instruction After Instruction A FF FFFF FFFF A FF FFFF FFFF B 00 0000 0001 B 00 0000 7FFF OVM Example 2 0 OVM A = rnd(A) Before Instruction A OVM 4-144 0 Assembly Language Instructions 00 7FFF FFFF 1 After Instruction A OVM 00 7FFF FFFF 1 SPRU179C Rotate Accumulator Left Syntax src = src \\ CARRY Operands src : Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 0 8 S 7 1 6 0 5 0 4 1 3 0 2 0 1 0 0 1 Execution (C) ³ src(0) (src(30–0)) ³ src(31–1) (src(31)) ³ C 0 ³ src(39–32) Status Bits Affected by C Affects C Description This instruction rotates each bit of src left 1 bit. The value of the carry bit, C, before the execution of the instruction is shifted into the LSB of src. Then, the MSB of src is shifted into C. The guard bits of src are cleared. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example A = A \\ CARRY Before Instruction After Instruction A A 00 6000 2468 C SPRU179C 5F B000 1234 0 C 1 Assembly Language Instructions 4-145 Rotate Accumulator Left Using TC Syntax roltc(src) Operands src: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 0 8 S 7 1 6 0 5 0 4 1 3 0 2 0 1 1 0 0 Execution (TC) ³ src(0) (src(30–0)) ³ src(31–1) (src(31)) ³ C 0 ³ src(39–32) Status Bits Affects C Affected by TC Description This instruction rotates each bit of src left 1 bit. The value of the TC bit before the execution of the instruction is shifted into the LSB of src. Then, the MSB of src is shifted into C. The guard bits of src are cleared. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example roltc(A) Before Instruction A C TC 4-146 81 C000 5555 Assembly Language Instructions After Instruction A 00 8000 AAAB x C 1 1 TC 1 SPRU179C Rotate Accumulator Right Syntax src = src // CARRY Operands src: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 0 8 S 7 1 6 0 5 0 4 1 3 0 2 0 1 0 0 0 Execution (C) ³ src(31) (src(31–1)) ³ src(30–0) (src(0)) ³ C 0 ³ src(39–32) Status Bits Affects C Affected by C Description This instruction rotates each bit of src right 1 bit. The value of the carry bit, C, before the execution of the instruction is shifted into the MSB of src. Then, the LSB of src is shifted into C. The guard bits of src are cleared. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example A = A // CARRY Before Instruction After Instruction A A 00 5800 091A C SPRU179C 7F B000 1235 0 C 1 Assembly Language Instructions 4-147 Repeat Next Instruction repeat(Smem) repeat(#K) repeat(#lk) Syntax 1: 2: 3: Operands Smem: Single data-memory operand 0 v K v 255 0 v lk v 65 535 Opcode 1: 15 0 14 1 13 0 12 0 11 0 10 1 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 1 13 1 12 0 11 1 10 1 9 0 8 0 7 K 6 K 5 K 4 K 3 K 2 K 1 K 0 K 15 1 14 1 13 1 12 1 11 0 10 0 9 0 8 0 7 0 6 1 5 1 4 1 3 0 2 0 1 0 0 0 2: 3: 16-bit constant Execution 1: (Smem) ³ RC 2: K ³ RC 3: lk ³ RC Status Bits None Description The repeat counter (RC) is loaded with the number of iterations when this instruction is executed. The number of iterations (n) is given in a 16-bit single data-memory operand Smem or an 8- or 16-bit constant, K or lk, respectively. The instruction following the repeat instruction is repeated n + 1 times. You cannot access RC while it decrements. Note: This instruction is not repeatable. Words Syntaxes 1 and 2: 1 word Syntax 3: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntax 1: 3 cycles Syntax 2: 1 cycle Syntax 3: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 4-148 Assembly Language Instructions SPRU179C Repeat Next Instruction Classes Syntax 1: Class 5A (see page 3-11) Syntax 1: Class 5B (see page 3-11) Syntax 2: Class 1 (see page 3-3) Syntax 3: Class 2 (see page 3-5) Example 1 repeat(@DAT127) ; DAT127 .EQU 0FFFh Before Instruction After Instruction RC 0 RC 000C DP 031 DP 031 Data Memory 0FFFh Example 2 0FFFh 000C repeat(#2) ; Repeat next instruction 3 times Before Instruction RC Example 3 0 After Instruction RC 0002 repeat(#1111h) ; Repeat next instruction 4370 times Before Instruction RC SPRU179C 000C 0 After Instruction RC Assembly Language Instructions 1111 4-149 Block Repeat Syntax [d]blockrepeat(pmad) Operands 0 v pmad v 65 535 Opcode 15 1 14 1 13 1 12 1 11 0 10 0 9 Z 8 0 7 0 6 1 5 1 4 1 3 0 2 0 1 1 0 0 16-bit constant Execution 1 ³ BRAF If (delayed) then (PC) + 4 ³ RSA Else (PC) + 2 ³ RSA pmad ³ REA Status Bits Affects BRAF Description This instruction repeats a block of instructions the number of times specified by the memory-mapped block-repeat counter (BRC). BRC must be loaded before the execution of this instruction. When this instruction is executed, the block-repeat start address register (RSA) is loaded with PC + 2 (or PC + 4 if you use the delayed instruction) and the block-repeat end address register (REA) is loaded with the program-memory address (pmad). This instruction is interruptible. Single-instruction repeat loops can be included as part of block repeat blocks. To nest block repeat instructions you must ensure that: - BRC, RSA, and REA are appropriately saved and restored. - The block-repeat active flag (BRAF) is properly set. In a delayed block repeat (specified by the d prefix), the two 1-word instructions or the one 2-word instruction following this instruction is fetched and executed. Note: Block repeat can be deactivated by clearing the BRAF bit. Far branch and far call instructions cannot be included in a repeat block of instructions. This instruction is not repeatable. Words 2 words Cycles 4 cycles 2 cycles (delayed) Classes Class 29A (see page 3-68) 4-150 Assembly Language Instructions SPRU179C Block Repeat Example 1 @BRC = #99 blockrepeat(end_block – 1) ; end_block = Bottom of Block Before Instruction After Instruction PC PC 1002 1234 BRC 0063 RSA 5678 RSA 1002 REA Example 2 1000 BRC 9ABC REA end_block – 1 @BRC = #99 ;execute the block 100 times dblockrepeat(end_block – 1) AR1 = data(POINTER) ; initialize pointer ; end_block ; Bottom of Block Before Instruction After Instruction PC PC 1004 1234 BRC 0063 RSA 5678 RSA 1004 REA SPRU179C 1000 BRC 9ABC REA end_block – 1 Assembly Language Instructions 4-151 Repeat Next Instruction And Clear Accumulator Syntax repeat(#lk), dst = 0 Operands dst: A (accumulator A) B (accumulator B) 0 v lk v 65 535 Opcode 15 1 14 1 13 1 12 1 11 0 10 0 9 0 8 D 7 0 6 1 5 1 4 1 3 0 2 0 1 0 0 1 16-bit constant Execution 0 ³ dst lk ³ RC Status Bits None Description This instruction clears dst and repeats the next instruction n + 1 times, where n is the value in the repeat counter (RC). The RC value is obtained from the 16-bit constant lk. Words 2 words Cycles 2 cycles Classes Class 2 (see page 3-5) Example repeat(#1023) , A = 0 ; Repeat the next instruction 1024 times Before Instruction A RC 4-152 Assembly Language Instructions 0F FE00 8000 0000 After Instruction A RC 00 0000 0000 03FF SPRU179C Reset Status Register Bit SBIT = 0 ST(N, SBIT) = 0 Syntax 1: 2: Operands 0 v SBIT v 15 N + 0 or 1 Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 N 8 0 7 1 6 0 5 1 4 1 3 S 2 B 1 I 0 T Execution 0 ³ STN(SBIT) Status Bits None Description This instruction clears the specified bit in status register 0 or 1 to a logic 0. N designates the status register to modify and SBIT specifies the bit to be modified. The name of a field in a status register can be used as an operand instead of the N and SBIT operands (see Example1). Note: This instruction is not repeatable. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 SXM = 0 ; SXM means: n=1 and SBIT=8 Before Instruction ST1 Example 2 35CD After Instruction ST1 st(1,8) = 0 Before Instruction ST1 SPRU179C 34CD 35CD After Instruction ST1 34CD Assembly Language Instructions 4-153 Store Accumulator Conditionally Syntax if (cond) Xmem = hi(src) << ASM Operands src: Xmem: A (accumulator A) B (accumulator B) Dual data-memory operand The following table lists the conditions (cond operand) for this instruction. Cond Condition Code Cond Description Condition Code AEQ (A) = 0 0101 BEQ (B) = 0 1101 ANEQ (A) 0 0 0100 BNEQ (B) 0 0 1100 AGT (A) u 0 0110 BGT (B) u 0 1110 AGEQ (A) w 0 0010 BGEQ (B) w 0 1010 ALT (A) t 0 0011 BLT (B) t 0 1011 ALEQ Opcode Description (A) v 0 0111 BLEQ (B) v 0 1111 15 1 14 0 13 0 12 1 11 1 10 1 9 1 8 S 7 X 6 X 5 X 4 X 3 C 2 O 1 N 0 D Execution If (cond) Then (src) << (ASM – 16) ³ Xmem Else (Xmem) ³ (Xmem) Status Bits Affected by ASM and SXM Description If the condition is true, this instruction stores src left-shifted by (ASM – 16). The shift value is in the memory location designated by Xmem. If the condition is false, the instruction reads Xmem and writes the value in Xmem back to the same address; thus, Xmem remains the same. Regardless of the condition, Xmem is always read and updated. Words 1 word Cycles 1 cycle Classes Class 15 (see page 3-34) 4-154 Assembly Language Instructions SPRU179C Store Accumulator Conditionally Example if (ALT) *AR3+0% = hi(A) << ASM Before Instruction A FF FE00 4321 After Instruction A FF FE00 4321 ASM 01 ASM 01 AR0 0002 AR0 0002 AR3 0202 AR3 0204 0101 0202h FC00 Data Memory 0202h SPRU179C Assembly Language Instructions 4-155 Saturate Accumulator Syntax saturate(src) Operands src: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 0 8 S 7 1 6 0 5 0 4 0 3 0 2 0 1 1 0 1 Execution Saturate (src) ³ src Status Bits Affects OVsrc Description Regardless of the OVM value, this instruction allows the saturation of the content of src on 32 bits. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 saturate(B) Before Instruction B OVB Example 2 71 2345 6789 x After Instruction B OVB Before Instruction OVA F8 1234 5678 x After Instruction A OVA FF 8000 0000 1 saturate(B) Before Instruction B OVB 4-156 1 saturate(A) A Example 3 00 7FFF FFFF Assembly Language Instructions 00 0012 3456 x After Instruction B OVB 00 0012 3456 0 SPRU179C Shift Accumulator Arithmetically Syntax dst = src <<C SHIFT Operands src, dst Opcode A (accumulator A) B (accumulator B) –16 v SHIFT v 15 15 1 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 0 6 1 5 1 4 S 3 H 2 I 1 F 0 T Execution If SHIFT < 0 Then (src((–SHIFT) – 1)) ³ C (src(39–0)) << SHIFT ³ dst If SXM = 1 Then (src(39)) ³ dst(39–(39 + (SHIFT + 1))) Else 0 ³ dst(39–(39 + (SHIFT + 1))) Else (src(39 – SHIFT)) ³ C (src) << SHIFT ³ dst 0 ³ dst((SHIFT – 1)–0) Status Bits Affected by SXM and OVM Affects C and OVdst (or OVsrc, if dst = src) Description This instruction arithmetically shifts src and stores the result in dst or src, if dst is not specified. The execution of the instruction depends on the SHIFT value: - If the SHIFT value is less than 0, the following occurs: 1) src((–SHIFT) – 1) is copied into the carry bit, C. 2) If SXM is 1, the instruction executes an arithmetic right shift and the MSB of the src is shifted into dst(39–(39 + (SHIFT + 1))). 3) If SXM is 0, 0 is written into dst(39–(39 + (SHIFT + 1))). - If the SHIFT value is greater than 0, the following occurs: 1) src(39 – SHIFT) is copied into the carry bit, C. 2) An arithmetic left shift is produced by the instruction. 3) 0 is written into dst((SHIFT – 1)–0). Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) SPRU179C Assembly Language Instructions 4-157 Shift Accumulator Arithmetically Example 1 B = A <<C –5 Before Instruction After Instruction A A FF 8765 0055 00 4321 1234 B FF FC3B 2802 C x C 1 SXM Example 2 FF 8765 0055 B 1 SXM 1 B = B <<C +5 Before Instruction B 80 AA00 1234 After Instruction B 15 4002 4680 C C 1 0 OVM 0 SXM 4-158 0 OVM 0 SXM 0 Assembly Language Instructions SPRU179C Shift Accumulator Conditionally (shiftc) Syntax shiftc(src) Operands src: Opcode 15 1 A (accumulator A) B (accumulator B) 14 1 13 1 12 1 11 0 10 1 9 0 8 S 7 1 6 0 5 0 4 1 3 0 2 1 1 0 0 0 Execution If (src) = 0 Then 1 ³ TC Else If (src(31)) XOR (src(30)) = 0 Then (two significant sign bits) 0 ³ TC (src) << 1 ³ src Else (only one sign bit) 1 ³ TC Status Bits Affects TC Description If src has two significant sign bits, this instruction shifts the 32-bit src left by 1 bit. If there are two sign bits, the test control (TC) bit is cleared to 0; otherwise, it is set to 1. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example shiftc(A) Before Instruction A TC SPRU179C FF FFFF F001 x After Instruction A FF FFFF E002 TC Assembly Language Instructions 0 4-159 Shift Accumulator Logically Syntax dst = src <<< SHIFT Operands src, dst: A (accumulator A) B (accumulator B) –16 v SHIFT v 15 Opcode 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 1 6 1 5 1 4 S 3 H 2 I 1 F 0 T Execution If SHIFT < 0 Then src((–SHIFT) – 1) ³ C src(31–0) << SHIFT ³ dst 0 ³ dst(39–(31 + (SHIFT + 1))) If SHIFT = 0 Then 0³C Else src(31 – (SHIFT – 1)) ³ C src((31 – SHIFT)–0) << SHIFT ³ dst 0 ³ dst((SHIFT – 1)–0) 0 dst(39–32) Status Bits Affects C Description This instruction logically shifts src and stores the result in dst or src, if dst is not specified. The guard bits of dst or src, if dst is not specified, are also cleared. The execution of the instruction depends on the SHIFT value: - If the SHIFT value is less than 0, the following occurs: 1) src((–SHIFT) – 1) is copied into the carry bit, C. 2) A logical right shift is produced by the instruction. 3) 0 is written into dst(39–(31 + (SHIFT + 1))). - If the SHIFT value is greater than 0, the following occurs: 1) src(31 – (SHIFT – 1)) is copied into the carry bit, C. 2) A logical left shift is produced by the instruction. 3) 0 is written into dst((SHIFT – 1)–0). Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) 4-160 Assembly Language Instructions SPRU179C Shift Accumulator Logically Example 1 B = A <<< –5 Before Instruction After Instruction A A FF 8765 0055 FF 8000 0000 B 00 043B 2802 C Example 2 FF 8765 0055 B 0 C 1 B = B <<< +5 Before Instruction After Instruction B B 00 4002 4680 C SPRU179C 80 AA00 1234 0 C 1 Assembly Language Instructions 4-161 Square Distance (sqdst) Syntax sqdst(Xmem, Ymem) Operands Xmem, Ymem: Opcode 15 1 14 1 13 1 Dual data-memory operands 12 0 11 0 10 0 9 1 8 0 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (A(32–16)) (A(32–16)) + (B) ³ B ((Xmem) – (Ymem)) << 16 ³ A Status Bits Affected by OVM, FRCT, and SXM Affects C, OVA, and OVB Description Used in repeat single mode, this instruction computes the square of the distance between two vectors. The high part of accumulator A (bits 32–16) is squared, the product is added to accumulator B, and the result is stored in accumulator B. Ymem is subtracted from Xmem, the difference is shifted 16 bits left, and the result is stored in accumulator A. The value to be squared (A(32–16)) is the value of the accumulator before the subtraction is executed by this instruction. Words 1 word Cycles 1 cycle Classes Class 7 (see page 3-14) Example sqdst(*AR3+,AR4+) Before Instruction A FF ABCD 0000 B 00 0000 0000 FRCT 0 After Instruction A FF FFAB 0000 B 00 1BB1 8229 FRCT 0 AR3 0100 AR3 0101 AR4 0200 AR4 0201 0100h 0055 0100h 0055 0200h 00AA 0200h 00AA Data Memory 4-162 Assembly Language Instructions SPRU179C Square Syntax dst = Smem * Smem [, T = Smem ] dst = square (Smem) [, T = Smem ] dst = hi(A) * hi(A) dst = square (hi(A)) 1: 2: Operands Smem: dst: Opcode Single data-memory operand A (accumulator A) B (accumulator B) 1: 15 0 14 0 13 1 12 0 11 0 10 1 9 1 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 1 13 1 12 1 11 0 10 1 9 0 8 D 7 1 6 0 5 0 4 0 3 1 2 1 1 0 0 1 2: Execution 1: (Smem) ³ T (Smem) (Smem) ³ dst 2: (A(32–16)) (A(32–16)) ³ dst Status Bits Affected by OVM and FRCT Affects OVsrc Description This instruction squares a single data-memory operand Smem or the high part of accumulator A (bits 32–16) and stores the result in dst. T is unaffected when accumulator A is used; otherwise, Smem is stored in T. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Syntax 1: Class 3A (see page 3-6) Syntax 1: Class 3B (see page 3-8) Syntax 2: Class 1 (see page 3-3) Assembly Language Instructions 4-163 Square Example 1 B = square(@30) Before Instruction After Instruction B 00 0000 01F4 B 00 0000 00E1 T 0003 T 000F FRCT 0 DP 006 FRCT DP 0 006 Data Memory 031Eh Example 2 000F 031Eh 000F B = square(hi(A)) Before Instruction After Instruction A 00 000F 0000 A 00 000F 0000 B 00 0101 0101 B 00 0000 01C2 FRCT 4-164 Assembly Language Instructions 1 FRCT 1 SPRU179C Square and Accumulate Syntax 1: 2: Operands Opcode src = src + square (Smem) [, T = Smem ] src += square (Smem) [, T = Smem ] src = src + Smem * Smem [, T = Smem ] src += Smem * Smem [, T = Smem ] Smem: src: 15 0 14 0 Single data-memory operand A (accumulator A) B (accumulator B) 13 1 12 1 11 1 10 0 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (Smem) ³ T (Smem) (Smem) ) (src) ³ src Status Bits Affected by OVM and FRCT Affects OVsrc Description This instruction stores the data-memory value Smem in T, then it squares Smem and adds the product to src. The result is stored in src. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example 1 B = B + square(@30) , T = @30 Before Instruction After Instruction B 00 0320 0000 B 00 0320 00E1 T 0003 T 000F FRCT DP 0 006 FRCT 0 DP 006 Data Memory 031Eh SPRU179C 000F 031Eh 000F Assembly Language Instructions 4-165 Square and Accumulate Example 2 A = A + square(*AR3+) , T = *AR3+ Before Instruction After Instruction A 00 0000 01F4 A 00 0000 02D5 T 0003 T 000F FRCT AR3 0 FRCT 0 031E AR3 031F 000F 031Eh 000F Data Memory 031Eh 4-166 Assembly Language Instructions SPRU179C Square and Subtract Syntax 1: 2: Operands Opcode src = src – square(Smem) [, T = Smem ] src – = square(Smem) [, T = Smem ] src = src – Smem * Smem [, T = Smem ] src – = Smem * Smem [, T = Smem ] Smem: src: 15 0 14 0 Single data-memory operand A (accumulator A) B (accumulator B) 13 1 12 1 11 1 10 0 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (Smem) ³ T (src) – (Smem) (Smem) ³ src Status Bits Affected by OVM and FRCT Affects OVsrc Description This instruction stores the data-memory value Smem in T, then it squares Smem and subtracts the product from src. The result is stored in src. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example 1 A = A – square(@9) , T = @9 Before Instruction After Instruction A 00 014B 5DB0 A 00 0000 0320 T 8765 T 1234 FRCT DP 0 006 FRCT 0 DP 006 Data Memory 0309h SPRU179C 1234 0309h 1234 Assembly Language Instructions 4-167 Square and Subtract Example 2 B = B – square(*AR3) , T = *AR3 Before Instruction After Instruction B 00 014B 5DB0 B 00 0000 0320 T 8765 T 1234 FRCT AR3 0 FRCT 0 0309 AR3 0309 1234 0309h 1234 Data Memory 0309h 4-168 Assembly Language Instructions SPRU179C Store Block Repeat Counter Conditionally Syntax if (cond) Xmem = BRC Operands Xmem: Dual data-memory operand The following table lists the conditions (cond operand) for this instruction. Cond Condition Code Cond Description Condition Code AEQ (A) = 0 0101 BEQ (B) = 0 1101 ANEQ (A) 0 0 0100 BNEQ (B) 0 0 1100 AGT (A) u 0 0110 BGT (B) u 0 1110 AGEQ (A) w 0 0010 BGEQ (B) w 0 1010 ALT (A) t 0 0011 BLT (B) t 0 1011 ALEQ Opcode Description (A) v 0 0111 BLEQ (B) v 0 1111 15 1 14 0 13 0 12 1 11 1 10 1 9 0 8 1 7 X 6 X 5 X 4 X 3 C 2 O 1 N 0 D Execution If (cond) Then (BRC) ³ Xmem Else (Xmem) ³ Xmem Status Bits None Description If the condition is true, this instruction stores the content of the block-repeat counter (BRC) in Xmem. If the condition is false, the instruction reads Xmem and writes the value in Xmem back to the same address; thus, Xmem remains the same. Regardless of the condition, Xmem is always read and updated. Words 1 word Cycles 1 cycle Classes Class 15 (see page 3-34) Example if (AGT) *AR5– = BRC Before Instruction A 00 70FF FFFF After Instruction A 00 70FF FFFF AR5 0202 AR5 0201 BRC 4321 BRC 4321 1234 0202h 4321 Data Memory 0202h SPRU179C Assembly Language Instructions 4-169 Set Status Register Bit SBIT = 1 ST(N, SBIT) = 1 Syntax 1: 2: Operands 0 v SBIT v 15 N = 0 or 1 Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 N 8 1 7 1 6 0 5 1 4 1 3 S 2 B 1 I 0 T Execution 1 ³ STN(SBIT) Status Bits None Description This instruction sets the specified bit in status register 0 or 1 to a logic 1. N designates the status register to modify and SBIT specifies the bit to be modified. The name of a field in a status register can be used as an operand instead of the N and SBIT operands (see Example 1). Note: This instruction is not repeatable. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example 1 SXM = 1 ; SXM means: N=1, SBIT=8 Before Instruction ST1 Example 2 34CD After Instruction ST1 st(1,8) = 1 Before Instruction ST1 4-170 35CD Assembly Language Instructions 34CD After Instruction ST1 35CD SPRU179C Store T, TRN, or Immediate Value Into Memory Smem = T Smem = TRN Smem = #lk Syntax 1: 2: 3: Operands Smem: Single data-memory operand –32 768 v lk v 32 767 Opcode 1: 15 1 14 0 13 0 12 0 11 1 10 1 9 0 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 0 13 0 12 0 11 1 10 1 9 0 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 1 13 1 12 1 11 0 10 1 9 1 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 2: 3: 16-bit constant Execution 1: (T) ³ Smem 2: (TRN) ³ Smem 3: lk ³ Smem Status Bits None Description This instruction stores the content of T, the transition register (TRN), or a 16-bit constant lk in data-memory location Smem. Words Syntaxes 1 and 2: 1 word Syntax 3: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1 and 2: 1 cycle Syntax 3: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes SPRU179C Syntaxes 1 and 2: Class 10A (see page 3-24) Syntaxes 1 and 2: Class 10B (see page 3-25) Syntax 3: Class 12A (see page 3-28) Syntax 3: Class 12B (see page 3-29) Assembly Language Instructions 4-171 Store T, TRN, or Immediate Value Into Memory Example 1 @0 = FFFFh Before Instruction DP 004 After Instruction DP 004 Data Memory 0200h Example 2 0101 0200h FFFF @5 = TRN Before Instruction DP TRN 004 After Instruction DP 004 1234 TRN 1234 0030 0205h 1234 Data Memory 0205h Example 3 *AR7– = T Before Instruction After Instruction T 4210 T 4210 AR7 0321 AR7 0320 1200 0321h 4210 Data Memory 0321h 4-172 Assembly Language Instructions SPRU179C Store Accumulator High Into Memory Smem = hi(src) Smem = hi(src) << ASM Xmem = hi(src) << SHFT Smem = hi(src) << SHIFT Syntax 1: 2: 3: 4: Operands src: Opcode 1: A (accumulator A) B (accumulator B) Smem: Single data-memory operand Xmem: Dual data-memory operand 0 v SHFT v 15 –16 v SHIFT v 15 15 1 14 0 13 0 12 0 11 0 10 0 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 0 13 0 12 0 11 0 10 1 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 0 13 0 12 1 11 1 10 0 9 1 8 S 7 X 6 X 5 X 4 X 3 S 2 H 1 F 0 T 15 0 14 1 13 1 12 0 11 1 10 1 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 0 0 0 0 1 1 0 S 0 1 1 S H I F T 2: 3: 4: (src) << (–16) ³ Smem (src) << (ASM – 16) ³ Smem (src) << (SHFT – 16) ³ Xmem (src) << (SHIFT – 16) ³ Smem Execution 1: 2: 3: 4: Status Bits Affected by SXM Description This instruction stores the high part of src (bits 31–16) in data-memory location Smem. The src is shifted left (as specified by ASM, SHFT, or SHIFT) and bits 31–16 of the shifted value are stored in data memory (Smem or Xmem). If SXM = 0, bit 39 of src is copied in the MSBs of the data-memory location. If SXM = 1, the sign-extended value with bit 39 of src is stored in the MSBs of the data-memory location after being right-shifted by the exceeding guard bit margin. The src remains unaffected. SPRU179C Assembly Language Instructions 4-173 Store Accumulator High Into Memory Notes: The following syntaxes are assembled as a different syntax in certain cases. - Syntax 3: If SHFT = 0, the instruction opcode is assembled as syntax 1. - Syntax 4: If SHIFT = 0, the instruction opcode is assembled as syntax 1. - Syntax 4: If 0 t SHIFT v15 and an indirect modifier is equal to one of the Xmem modes, the instruction opcode is assembled as syntax 3. Words Syntaxes 1, 2, and 3: 1 word Syntax 4: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1, 2, and 3: 1 cycle Syntax 4: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntaxes 1, 2, and 3: Class 10A (see page 3-24) Syntaxes 1 and 2: Class 10B (see page 3-25) Syntax 4: Class 11A (see page 3-26) Syntax 4: Class 11B (see page 3-27) Example 1 @10 = hi(A) Before Instruction A FF 8765 4321 DP 004 After Instruction A DP FF 8765 4321 004 Data Memory 020Ah Example 2 1234 020Ah 8765 *AR7– = hi(B) << (–8) Before Instruction B AR7 FF 8421 1234 After Instruction B FF 8421 1234 0321 AR7 0320 ABCD 0321h FF84 Data Memory 0321h 4-174 Assembly Language Instructions SPRU179C Store Accumulator High Into Memory Example 3 @10 = hi(A) << (–4) Before Instruction A SXM DP FF 8421 1234 1 004 After Instruction A FF 8421 1234 SXM DP 1 004 Data Memory 020Ah SPRU179C 7FFF 020Ah Assembly Language Instructions F842 4-175 Store Accumulator Low Into Memory Smem = src Smem = src << ASM Xmem = src << SHFT Smem = src << SHIFT Syntax 1: 2: 3: 4: Operands src: A (accumulator A) B (accumulator B) Smem: Single data-memory operand Xmem: Dual data-memory operand 0 v SHFT v 15 –16 v SHIFT v 15 Opcode 1: 15 1 14 0 13 0 12 0 11 0 10 0 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 0 13 0 12 0 11 0 10 1 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 0 13 0 12 1 11 1 10 0 9 0 8 S 7 X 6 X 5 X 4 X 3 S 2 H 1 F 0 T 15 0 14 1 13 1 12 0 11 1 10 1 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A A 0 0 0 0 1 1 0 S 1 0 0 S H I F T 2: 3: 4: 0 (src) ³ Smem (src) << ASM ³ Smem (src) << SHFT ³ Xmem (src) << SHIFT ³ Smem Execution 1: 2: 3: 4: Status Bits Affected by SXM Description This instruction stores the low part of src (bits 15–0) in data-memory location Smem. The src is shifted left (as specified by ASM, SHFT, or SHIFT) and bits 15–0 of the shifted value are stored in data memory (Smem or Xmem). When the shifted value is positive, zeros are shifted into the LSBs. 4-176 Assembly Language Instructions SPRU179C Store Accumulator Low Into Memory Notes: The following syntaxes are assembled as a different syntax in certain cases. - Syntax 3: If SHFT = 0, the instruction opcode is assembled as syntax 1. - Syntax 4: If SHIFT = 0, the instruction opcode is assembled as syntax 1. - Syntax 4: If 0 t SHIFT v15 and an indirect modifier is equal to one of the Xmem modes, the instruction opcode is assembled as syntax 3. Words Syntaxes 1, 2, and 3: 1 word Syntax 4: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1, 2, and 3: 1 cycle Syntax 4: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntaxes 1, 2, and 3: Class 10A (see page 3-24) Syntaxes 1, 2, and 3: Class 10B (see page 3-25) Syntax 4: Class 11A (see page 3-26) Syntax 4: Class 11B (see page 3-27) Example 1 @11 = A Before Instruction A After Instruction A FF 8765 4321 DP 004 FF 8765 4321 DP 004 Data Memory 020Bh Example 2 1234 020Bh 4321 *AR7– = B << (–8) Before Instruction B FF 8421 1234 After Instruction B FF 8421 1234 SXM 0 SXM 0 AR7 0321 AR7 0320 0099 0321h 2112 Data Memory 0321h SPRU179C Assembly Language Instructions 4-177 Store Accumulator Low Into Memory Example 3 @11 = A << 7 Before Instruction A DP FF 8421 1234 004 After Instruction A DP FF 8421 1234 004 Data Memory 020Bh 4-178 Assembly Language Instructions 0101 020Bh 1A00 SPRU179C Store Accumulator Low Into Memory-Mapped Register Syntax 1: 2: Operands MMR = src mmr(MMR) = src src: A (accumulator A) B (accumulator B) Memory-mapped register MMR: Opcode 15 1 14 0 13 0 12 0 11 1 10 0 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (src(15–0)) ³ MMR Status Bits None Description This instruction stores the low part of src (bits 15–0) into the addressed memory-mapped register MMR. The nine MSBs of the effective address are cleared to 0 regardless of the current value of DP or of the upper nine bits of ARx. This instruction allows src to be stored in any memory location on data page 0 without modifying the DP field in status register ST0. Words 1 word Cycles 1 cycle Classes Class 10A (see page 3-24) Example 1 BRC = A Before Instruction A BRC(1Ah) Example 2 FF 8765 4321 1234 After Instruction A FF 8765 4321 BRC 4321 mmr(*AR1–) = B Before Instruction B FF 8421 1234 After Instruction B FF 8421 1234 AR1 AR1 0016 AR7(17h) SPRU179C 3F17 0099 AR7 1234 Assembly Language Instructions 4-179 Store Immediate Value Into Memory-Mapped Register MMR = #lk mmr(MMR) = #lk Syntax 1: 2: Operands MMR: Memory-mapped register –32 768 v lk v 32 767 Opcode 15 0 14 1 13 1 12 1 11 0 10 1 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 16-bit constant Execution lk ³ MMR Status Bits None Description This instruction stores a 16-bit constant lk into a memory-mapped register MMR or a memory location on data page 0 without modifying the DP field in status register ST0. The nine MSBs of the effective address are cleared to 0 regardless of the current value of DP or of the upper nine bits of ARx. Words 2 words Cycles 2 cycles Classes Class 12A (see page 3-28) Example 1 IMR = #0FFFFh Before Instruction IMR Example 2 FF01 After Instruction IMR FFFF mmr(*AR7+) = #8765h Before Instruction After Instruction AR0 AR0 8765 AR7 4-180 0000 8010 AR7 0011 Assembly Language Instructions SPRU179C Store Accumulator With Parallel Add Syntax Ymem = hi(src) [ << ASM ] || dst = dst_ + Xmem << 16 Operands src, dst: A (accumulator A) B (accumulator B) Dual data-memory operands If dst = A, then dst_ = B; if dst = B, then dst_ = A Xmem, Ymem: dst_: Opcode 15 1 14 1 13 0 12 0 11 0 10 0 9 S 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (src) << (ASM * 16) ³ Ymem (dst_ ) ) (Xmem) << 16 ³ dst Status Bits Affected by OVM, SXM, and ASM Affects C and OVdst Description This instruction stores src shifted by (ASM – 16) in data-memory location Ymem. In parallel, this instruction adds the content of dst_ to the data-memory operand Xmem shifted left 16 bits, and stores the result in dst. If src is equal to dst, the value stored in Ymem is the value of src before the execution. Words 1 word Cycles 1 cycle Classes Class 14 (see page 3-32) Example *AR3 = hi(A) ||B = A + *AR5+0% << 16 Before Instruction After Instruction A FF 8421 1000 A FF 8021 1000 B 00 0000 1111 B FF 0422 1000 OVM 0 OVM 0 SXM 1 SXM 1 ASM 1 ASM 1 AR0 0002 AR0 0002 AR3 0200 AR3 0200 AR5 0300 AR5 0302 0200h 0101 0200h 0842 0300h 8001 0300h 8001 Data Memory SPRU179C Assembly Language Instructions 4-181 Store Accumulator With Parallel Load Syntax Ymem = hi(src) [ << ASM ] || dst = Xmem << 16 Ymem = hi(src) [ << ASM ] || T = Xmem 1: 2: Operands src, dst: Xmem, Ymem: Opcode A (accumulator A) B (accumulator B) Dual data-memory operands 1: 15 1 14 1 13 0 12 0 11 1 10 0 9 S 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y 15 1 14 1 13 1 12 0 11 0 10 1 9 S 8 0 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y 2: Execution 1. (src) << (ASM * 16) ³ Ymem (Xmem) << 16 ³ dst 2. (src) << (ASM * 16) ³ Ymem (Xmem) ³ T Status Bits Affected by OVM and ASM Affects C Description This instruction stores src shifted by (ASM – 16) in data-memory location Ymem. In parallel, this instruction loads the 16-bit dual data-memory operand Xmem to dst or T. If src is equal to dst, the value stored in Ymem is the value of src before the execution. Words 1 word Cycles 1 cycle Classes Class 14 (see page 3-32) 4-182 Assembly Language Instructions SPRU179C Store Accumulator With Parallel Load Example 1 *AR2– = hi(B) ||A = *AR4+ << 16 Before Instruction After Instruction A 00 0000 001C A FF 8001 0000 B FF 8421 1234 B FF 8421 1234 SXM 1 SXM 1 ASM 1C ASM 1C AR2 01FF AR2 01FE AR4 0200 AR4 0201 01FFh xxxx 01FFh F842 0200h 8001 0200h 8001 Data Memory Example 2 *AR3 = hi(A) ||T = *AR4 Before Instruction After Instruction A FF 8421 1234 A FF 8421 1234 T 3456 T 80FF ASM 1 ASM 1 AR3 0200 AR3 0200 AR4 0100 AR4 0100 0200h 0001 0200h 0842 0100h 80FF 0100h 80FF Data Memory Example 3 *AR2+ = hi(A) ||A = *AR2– << 16 In Example 3, the load reads the source operand at the memory location pointed to by AR2 before the store writes to the same location. The store reads the source operand of accumulator A before load loads accumulator A. SPRU179C Assembly Language Instructions 4-183 Store Accumulator With Parallel Multiply Accumulate With/Without Rounding Syntax 1: 2: 3: Operands Ymem = hi(src) [ << ASM ] || dst = dst + T * Xmem Ymem = hi(src) [ << ASM ] || dst += T * Xmem Ymem = hi(src) [ << ASM ] || dst = rnd(dst + T * Xmem) src, dst: A (accumulator A) B (accumulator B) Dual data-memory operands Xmem, Ymem: Opcode 15 1 14 1 13 0 12 1 11 0 10 R 9 S 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (src << (ASM – 16)) ³ Ymem If (Rounding) Then Round ((Xmem) (T) + (dst)) ³ dst Else (Xmem) (T) + (dst) ³ dst Status Bits Affected by OVM, SXM, ASM, and FRCT Affects C and OVdst Description This instruction stores src shifted by (ASM – 16) in data-memory location Ymem. In parallel, this instruction multiplies the content of T by the datamemory operand Xmem, adds the value in dst (with or without rounding), and stores the result in dst. If src is equal to dst, the value stored in Ymem is the value of src before the execution of this instruction. If you use the rnd prefix, this instruction rounds the result of the multiply accumulate operation by adding 215 to the result and clearing the LSBs (bits 15–0) to 0. Words 1 word Cycles 1 cycle Classes Class 14 (see page 3-32) 4-184 Assembly Language Instructions SPRU179C Store Accumulator With Parallel Multiply Accumulate With/Without Rounding Example 1 *AR4– = hi(A) ||B = B + *AR5 * T Before Instruction After Instruction A 00 0011 1111 A 00 0011 1111 B 00 0000 1111 B 00 010C 9511 T 0400 T 0400 ASM 5 ASM 5 FRCT 0 FRCT 0 AR4 0100 AR4 00FF AR5 0200 AR5 0200 100h 1234 100h 0222 200h 4321 200h 4321 Data Memory Example 2 *AR4+ = hi(A) ||B = rnd(B + *AR5+ * T) Before Instruction After Instruction A 00 0011 1111 A 00 0011 1111 B 00 0000 1111 B 00 010D 0000 T 0400 T 0400 ASM 1C ASM 1C FRCT 0 FRCT 0 AR4 0100 AR4 0101 AR5 0200 AR5 0201 100h 1234 100h 0001 200h 4321 200h 4321 Data Memory SPRU179C Assembly Language Instructions 4-185 Store Accumulator With Parallel Multiply Subtract With/Without Rounding Syntax 1: 2: 3: Operands Ymem = hi(src) [ << ASM ] || dst = dst – T * Xmem Ymem = hi(src) [ << ASM ] || dst – = T * Xmem Ymem = hi(src) [ << ASM ] || dst = rnd(dst – T * Xmem) src, dst: A (accumulator A) B (accumulator B) Dual data-memory operands Xmem, Ymem: Opcode 15 1 14 1 13 0 12 1 11 1 10 R 9 S 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (src << (ASM * 16)) ³ Ymem If (Rounding) Then Round ((dst) – (Xmem) (T))³ dst Else (dst) – (Xmem) (T) ³ dst Status Bits Affected by OVM, SXM, ASM, and FRCT Affects C and OVdst Description This instruction stores src shifted by (ASM – 16) in data-memory location Ymem. In parallel, this instruction multiplies the content of T by the datamemory operand Xmem, subtracts the value from dst (with or without rounding), and stores the result in dst. If src is equal to dst, the value stored in Ymem is the value of src before the execution of this instruction. If you use the rnd prefix, this instruction optionally rounds the result of this operation by adding 215 to the result and clearing the LSBs (bits 15–0) to 0. Words 1 word Cycles 1 cycle Classes Class 14 (see page 3-32) 4-186 Assembly Language Instructions SPRU179C Store Accumulator With Parallel Multiply Subtract With/Without Rounding Example 1 *AR4+ = hi(A) ||B = B – *AR5 * T Before Instruction After Instruction A 00 0011 1111 A 00 0011 1111 B 00 0000 1111 B FF FEF3 8D11 T 0400 T 0400 ASM 5 ASM 5 FRCT 0 FRCT 0 AR4 0100 AR4 0101 AR5 0200 AR5 0200 0100h 1234 0100h 0222 0200h 4321 0200h 4321 Data Memory Example 2 *AR4+ = hi(A) ||B = rnd(B – *AR5+ * T) Before Instruction After Instruction A 00 0011 1111 A 00 0011 1111 B 00 0000 1111 B FF FEF4 0000 T 0400 T 0400 ASM FRCT 1 ASM 0 FRCT 1 0 AR4 0100 AR4 0101 AR5 0200 AR5 0201 0100h 1234 0100h 0022 0200h 4321 0200h 4321 Data Memory SPRU179C Assembly Language Instructions 4-187 Store Accumulator With Parallel Multiply Syntax Ymem = hi(src) [ << ASM ] || dst = T * Xmem Operands src, dst: A (accumulator A) B (accumulator B) Dual data-memory operands Xmem, Ymem: Opcode 15 1 14 1 13 0 12 0 11 1 10 1 9 S 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (src << (ASM * 16)) ³ Ymem (T) (Xmem) ³ dst Status Bits Affected by OVM, SXM, ASM, and FRCT Affects C and OVdst Description This instruction stores src shifted by (ASM – 16) in data-memory location Ymem. In parallel, this instruction multiplies the content of T by the 16-bit dual data-memory operand Xmem, and stores the result in dst. If src is equal to dst, then the value stored in Ymem is the value of src before the execution. Words 1 word Cycles 1 cycle Classes Class 14 (see page 3-32) Example *AR3+ = hi(A) ||B = T * *AR5+ Before Instruction After Instruction A FF 8421 1234 A FF 8421 1234 B xx xxxx xxxx B 00 2000 0000 T 4000 T 4000 ASM FRCT 00 ASM 1 FRCT 00 1 AR3 0200 AR3 0201 AR5 0300 AR5 0301 0200h 1111 0200h 8421 0300h 4000 0300h 4000 Data Memory 4-188 Assembly Language Instructions SPRU179C Store Accumulator With Parallel Subtract Syntax Ymem = hi(src) [ << ASM ] || dst = Xmem << 16 – dst_ Operands src, dst: A (accumulator A) B (accumulator B) Dual data-memory operands If dst = A, then dst_ = B; if dst = B, then dst_ = A. Xmem, Ymem: dst_: Opcode 15 1 14 1 13 0 12 0 11 0 10 1 9 S 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y Execution (src << (ASM * 16)) ³ Ymem (Xmem) << 16 – (dst_ ) ³ dst Status Bits Affected by OVM, SXM, and ASM Affects C and OVdst Description This instruction stores src shifted by (ASM – 16) in data-memory location Ymem. In parallel, this instruction subtracts the content of dst_ from the 16-bit dual data-memory operand Xmem shifted left 16 bits, and stores the result in dst. If src is equal to dst, then the value stored in Ymem is the value of src before the execution. Words 1 word Cycles 1 cycle Classes Class 14 (see page 3-32) Example *AR3– = hi(A) ||B = *AR5+0% << 16 – A Before Instruction After Instruction A FF 8421 0000 A FF 8421 0000 B 00 1000 0001 B FF FBE0 0000 ASM 01 ASM SXM 1 SXM 1 AR0 0002 AR0 0002 AR3 01FF AR3 01FE AR5 0300 AR5 0302 01FFh 1111 01FFh 0842 0300h 8001 0300h 8001 01 Data Memory SPRU179C Assembly Language Instructions 4-189 Store T Conditionally Syntax if (cond) Xmem = T Operands Xmem: Dual data-memory operand The following table lists the conditions (cond operand) for this instruction. Cond Condition Code Cond Description Condition Code AEQ (A) = 0 0101 BEQ (B) = 0 1101 ANEQ (A) 0 0 0100 BNEQ (B) 0 0 1100 AGT (A) u 0 0110 BGT (B) u 0 1110 AGEQ (A) w 0 0010 BGEQ (B) w 0 1010 ALT (A) t 0 0011 BLT (B) t 0 1011 ALEQ Opcode Description (A) v 0 0111 BLEQ (B) v 0 1111 15 1 14 0 13 0 12 1 11 1 10 1 9 0 8 0 7 X 6 X 5 X 4 X 3 C 2 O 1 N 0 D Execution If (cond) (T) ³ Xmem Else (Xmem) ³ Xmem Status Bits None Description If the condition is true, this instruction stores the content of T into the datamemory location Xmem. If the condition is false, the instruction reads Xmem and writes the value in Xmem back to the same address; thus, Xmem remains the same. Regardless of the condition, Xmem is always read and updated. Words 1 word Cycles 1 cycle Classes Class 15 (see page 3-34) Example if (AGT) *AR5– = T Before Instruction After Instruction A 00 70FF FFFF A 00 70FF FFFF T 4321 T 4321 AR5 0202 AR5 0201 1234 0202h 4321 Data Memory 0202h 4-190 Assembly Language Instructions SPRU179C Subtract From Accumulator src = src – Smem src – = Smem 2: src = src – Smem << TS src – = Smem << TS dst = src – Smem << 16 3: dst – = Smem << 16 dst = src – Smem [ << SHIFT ] 4: dst – = Smem [ << SHIFT ] 5: src = src – Xmem << SHFT src – = Xmem << SHFT 6: dst = Xmem << 16 – Ymem << 16 dst = src – #lk [ << SHFT ] 7: dst – = #lk [ << SHFT ] dst = src – #lk << 16 8: dst – = #lk << 16 dst = dst – src << SHIFT 9: dst – = src << SHIFT 10: dst = dst – src << ASM dst – = src << ASM Syntax 1: Operands src, dst: Opcode 1: A (accumulator A) B (accumulator B) Smem: Single data-memory operand Xmem, Ymem: Dual data-memory operands –32 768 v lk v 32 767 0 v SHFT v 15 –16 v SHIFT v 15 15 0 14 0 13 0 12 0 11 1 10 0 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 0 13 0 12 0 11 1 10 1 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 1 13 0 12 0 11 0 10 0 9 S 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 0 14 1 13 1 12 0 11 1 10 1 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 0 0 0 0 1 1 S D 0 0 1 S H I F T 2: 3: 4: SPRU179C Assembly Language Instructions 4-191 Subtract From Accumulator 5: 15 1 14 0 13 0 12 1 11 0 10 0 9 1 8 S 7 X 6 X 5 X 4 X 3 S 2 H 1 F 0 T 15 1 14 0 13 1 12 0 11 0 10 0 9 1 8 D 7 X 6 X 5 X 4 X 3 Y 2 Y 1 Y 0 Y 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 6 0 5 0 4 1 3 S 2 H 1 F 0 T 6 1 5 1 4 0 3 0 2 0 1 0 0 1 6: 7: 16-bit constant 8: 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 16-bit constant 9: 15 1 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 0 6 0 5 1 4 S 3 H 2 I 1 F 0 T 14 1 13 1 12 1 11 0 10 1 9 S 8 D 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 1 10: 15 1 (src) – (Smem) ³ src (src) – (Smem) << TS ³ src (src) – (Smem) << 16 ³ dst (src) – (Smem) << SHIFT ³ dst (src) – (Xmem) << SHFT ³ src (Xmem) << 16 – (Ymem) << 16 ³ dst (src) – lk << SHFT ³ dst (src) – lk << 16 ³ dst (dst) – (src) << SHIFT ³ dst (dst) – (src) << ASM ³ dst Execution 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: Status Bits Affected by SXM and OVM Affects C and OVdst or OVsrc For instruction syntax 3, if the result of the subtraction generates a borrow, the carry bit, C, is cleared to 0; otherwise, C is not affected. 4-192 Assembly Language Instructions SPRU179C Subtract From Accumulator Description This instruction subtracts a 16-bit value from the content of the selected accumulator or from the 16-bit operand Xmem in dual data-memory addressing mode. The 16-bit value to be subtracted is one of the following: - The content of a single data-memory operand (Smem) The content of a dual data-memory operand (Ymem) A 16-bit immediate operand (#lk) The shifted value in src If a dst is specified, this instruction stores the result in dst. If no dst is specified, this instruction stores the result in src. Most of the second operands can be shifted. For a left shift: - Low-order bits are cleared - High-order bits are: J J Sign extended if SXM = 1 Cleared if SXM = 0 For a right shift, the high-order bits are: J J Sign extended if SXM = 1 Cleared if SXM = 0 Notes: The following syntaxes are assembled as a different syntax in certain cases. - Syntax 4: If dst = src and SHIFT = 0, then the instruction opcode is assembled as syntax 1. - Syntax 4: If dst = src, SHIFT v 15, and Smem indirect addressing mode is included in Xmem, then the instruction opcode is assembled as syntax 1. Words Syntaxes 1, 2, 3, 5, 6, 9, and 10: 1 word Syntaxes 4, 7, and 8: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1, 2, 3, 5, 6, 9, and 10: 1 cycle Syntaxes 4, 7, and 8: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. SPRU179C Assembly Language Instructions 4-193 Subtract From Accumulator Classes Syntaxes 1, 2, 3, and 5: Class 3A (see page 3-6) Syntaxes 1, 2, and 3: Class 3B (see page 3-8) Syntax 4: Class 4A (see page 3-9) Syntax 4: Class 4B (see page 3-10) Syntax 6: Class 7 (see page 3-14) Syntaxes 7 and 8: Class 2 (see page 3-5) Syntaxes 9 and 10: Class 1 (see page 3-3) Example 1 A = A – *AR1+ << 14 Before Instruction After Instruction A 00 0000 1200 A FF FAC0 1200 C x C 0 SXM 1 SXM 1 AR1 0100 AR1 0101 1500 0100h 1500 Data Memory 0100h Example 2 B = B – A << –8 Before Instruction A 00 0000 1200 After Instruction A 00 0000 1200 B B 00 0000 17EE x C 1 SXM Example 3 00 0000 1800 C 1 SXM 1 B = A – #12345 << 8 Before Instruction After Instruction A A 00 0000 1200 00 0000 1800 B FF FFCF D900 C x C 0 SXM 4-194 00 0000 1200 B 1 SXM 1 Assembly Language Instructions SPRU179C Subtract From Accumulator With Borrow Syntax src = src – Smem – BORROW src – = Smem – BORROW Operands src: Smem: Opcode 15 0 14 0 A (accumulator A) B (accumulator B) Single data-memory operand 13 0 12 0 11 1 10 1 9 1 8 D 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (src) – (Smem) – (logical inversion of C) ³ src Status Bits Affected by OVM and C Affects C and OVsrc Description This instruction subtracts the content of the 16-bit single data-memory operand Smem and the logical inverse of the carry bit, C, from src without sign extension. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example 1 A = A – @5 – BORROW Before Instruction After Instruction A 00 0000 0006 A FF FFFF FFFF C 0 C 0 DP 008 DP 008 Data Memory 0405h Example 2 0006 0405h 0006 B = B – *AR1+ – BORROW Before Instruction B FF 8000 0006 After Instruction B FF 8000 0000 C 1 C 1 OVM 1 OVM 1 AR1 0405 AR1 0406 0006 0405h 0006 Data Memory 0405h SPRU179C Assembly Language Instructions 4-195 Subtract Conditionally (subc) Syntax subc(Smem, src) Operands Smem: src: Opcode 15 0 14 0 Single data-memory operand A (accumulator A) B (accumulator B) 13 0 12 1 11 1 10 1 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution (src) – ((Smem) << 15) ³ ALU output If ALU output w 0 Then ((ALU output) << 1) + 1 ³ src Else (src) << 1 ³ src Status Bits Affected by SXM Affects C and OVsrc Description This instruction subtracts the 16-bit single data-memory operand Smem, leftshifted 15 bits, from the content of src. If the result is greater than 0, it is shifted 1 bit left, 1 is added to the result, and the result is stored in src. Otherwise, this instruction shifts the content of src 1 bit left and stores the result in src. The divisor and the dividend are both assumed to be positive in this instruction. The SXM bit affects this operation in these ways: - If SXM = 1, the divisor must have a 0 value in the MSB. - If SXM = 0, any 16-bit divisor value produces the expected results. The dividend, which is in src, must initially be positive (bit 31 must be 0) and must remain positive following the accumulator shift, which occurs in the first portion of the instruction. This instruction affects OVA or OVB (depending on src) but is not affected by OVM; therefore, src does not saturate on positive or negative overflows when executing this instruction. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. 4-196 Assembly Language Instructions SPRU179C Subtract Conditionally Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example 1 subc(@2,A) Before Instruction After Instruction A 00 0000 0004 A 00 0000 0008 C x C 0 DP 006 DP 006 Data Memory 0302h Example 2 0001 0302h 0001 repeat(#15) subc(*AR1,B) Before Instruction After Instruction B 00 0000 0041 B 00 0002 0009 C x C 1 AR1 1000 AR1 1000 0007 1000h 0007 Data Memory 1000h SPRU179C Assembly Language Instructions 4-197 Subtract From Accumulator With Sign Extension Suppressed Syntax src = src – uns(Smem) src – = uns(Smem) Operands Smem: src: Opcode 15 0 14 0 Single data-memory operand A (accumulator A) B (accumulator B) 13 0 12 0 11 1 10 0 9 1 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution src – unsigned (Smem) ³ src Status Bits Affected by OVM Affects C and OVsrc Description This instruction subtracts the content of the 16-bit single data-memory operand Smem from the content of src. Smem is considered a 16-bit unsigned number regardless of the value of SXM. The result is stored in src. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 1 cycle Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 3A (see page 3-6) Class 3B (see page 3-8) Example B = B – uns(*AR2–) Before Instruction After Instruction B 00 0000 0002 B FF FFFF 0FFC C x C 0 AR2 0100 AR2 00FF F006 0100h F006 Data Memory 0100h 4-198 Assembly Language Instructions SPRU179C Software Interrupt (trap) Syntax trap(K) Operands 0 v K v 31 Opcode 15 1 14 1 13 1 12 1 11 0 10 1 9 0 8 0 7 1 6 1 5 0 4 K 3 K 2 K 1 K 0 K Execution (SP) * 1 ³ SP (PC) ) 1 ³ TOS Interrupt vector specified by K ³ PC Status Bits None Description This instruction transfers program control to the interrupt vector specified by K. This instruction allows you to use your software to execute any interrupt service routine. For a list of interrupts and their corresponding K value, see your device datasheet. This instruction pushes PC + 1 onto the data-memory location addressed by SP. This enables a return instruction to retrieve the pointer to the instruction after the trap from the data-memory location addressed by SP. This instruction is not maskable and is not affected by INTM nor does it affect INTM. Note: This instruction is not repeatable. Words 1 word Cycles 3 cycles Classes Class 35 (see page 3-74) Example trap(10h) Before Instruction After Instruction PC 1233 PC FFC0 SP 03FF SP 03FE 03FEh 9653 03FEh 1234 Data Memory SPRU179C Assembly Language Instructions 4-199 Write Data to Program Memory Addressed by Accumulator A Syntax prog(A) = Smem Operands Smem: Opcode 15 0 14 1 Single data-memory operand 13 1 12 1 11 1 10 1 9 1 8 1 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution A ³ PAR If (RC) 0 0 Then (Smem) ³ (Pmem addressed by PAR) (PAR) + 1 ³ PAR (RC) – 1 ³ RC Else (Smem) ³ (Pmem addressed by PAR) Status Bits None Description This instruction transfers a word from a data-memory location specified by Smem to a program-memory location. The program-memory location is defined by accumulator A, depending on the specific device, as follows: C541–C546 Devices with Extended Program Memory A(15–0) A(22–0) This instruction can be used with the repeat instruction to move consecutive words (using indirect addressing) in data memory to a continuous programmemory space addressed by PAR by automatically incrementing PAR. The initial value is set with the 16 LSBs of accumulator A. The source and destination blocks in memory do not have to be entirely on-chip or off-chip. When used with repeat, this instruction becomes a single-cycle instruction once the repeat pipeline is started. The content of accumulator A is not affected by this instruction. Words 1 word Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 5 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes 4-200 Class 26A (see page 3-62) Class 26B (see page 3-64) Assembly Language Instructions SPRU179C Write Data to Program Memory Addressed by Accumulator A Example prog(A) = @5 Before Instruction A DP 00 0000 0257 032 After Instruction A 00 0000 0257 DP 032 Program Memory 0257h 0306 0257h 4339 4339 1005h 4339 Data Memory 1005h SPRU179C Assembly Language Instructions 4-201 Execute Conditionally Syntax if (cond [, cond [, cond ] ] ) execute(n) Operands n + 1 or 2 The following table lists the conditions (cond operand) for this instruction. Cond Condition Code Cond Description Condition Code BIO BIO low 0000 0011 NBIO BIO high 0000 0010 C C=1 0000 1100 NC C=0 0000 1000 TC TC = 1 0011 0000 NTC TC = 0 0010 0000 AEQ (A) = 0 0100 0101 BEQ (B) = 0 0100 1101 ANEQ (A) 0 0 0100 0100 BNEQ (B) 0 0 0100 1100 AGT (A) u 0 0100 0110 BGT (B) u 0 0100 1110 AGEQ (A) w 0 0100 0010 BGEQ (B) w 0 0100 1010 ALT (A) t 0 0100 0011 BLT (B) t 0 0100 1011 ALEQ (A) v 0 0100 0111 BLEQ (B) v 0 0100 1111 AOV A overflow 0111 0000 BOV B overflow 0111 1000 ANOV A no overflow 0110 0000 BNOV B no overflow 0110 1000 UNC Opcode Description Unconditional 0000 0000 15 1 14 1 13 1 12 1 11 1 10 1 9 N 8 1 7 C 6 C Syntax n 3 C 2 C 1 C 0 C 0 2 4 C Opcode N 1 5 C 1 Execution If (cond) Then Next n instructions are executed Else Execute nop for next n instructions Status Bits None 4-202 Assembly Language Instructions SPRU179C Execute Conditionally Description The execution of this instruction depends on the value of n and the selected conditions: - If n = 1 and the condition(s) is met, the 1-word instruction following this instruction is executed. - If n = 2 and the condition(s) is met, the one 2-word instruction or the two 1-word instructions following this instruction are executed. - If the condition(s) is not met, one or two nops are executed depending on the value of n. This instruction tests multiple conditions before executing and can test the conditions individually or in combination with other conditions. You can combine conditions from only one group as follows: Group 1: You can select up to two conditions. Each of these conditions must be from a different category (category A or B); you cannot have two conditions from the same category. For example, you can test EQ and OV at the same time but you cannot test GT and NEQ at the same time. The accumulator must be the same for both conditions; you cannot test conditions for both accumulators with the same instruction. For example, you can test AGT and AOV at the same time, but you cannot test AGT and BOV at the same time. Group 2: You can select up to three conditions. Each of these conditions must be from a different category (category A, B, or C); you cannot have two conditions from the same category. For example, you can test TC, C, and BIO at the same time but you cannot test NTC, C, and NC at the same time. Conditions for This Instruction Group 2 Group 1 Category A Category B Category A Category B Category C EQ OV TC C BIO NEQ NOV NTC NC NBIO LT LEQ GT GEQ This instruction and the two instruction words following this instruction are uninterruptible. SPRU179C Assembly Language Instructions 4-203 Execute Conditionally Note: The conditions tested are sampled two full cycles before this instruction is executed. Therefore, if the two 1-word instructions or one 2-word instruction modifies the conditions, there is no effect on the execution of this instruction, but if the conditions are modified during the two slots, the interrupt operation using this instruction can cause undesirable results. This instruction is not repeatable. Words 1 word Cycles 1 cycle Classes Class 1 (see page 3-3) Example if (ALEQ) execute (1) mar(*AR1+) A = A + A << DAT100 Before Instruction A AR1 FF FFFF FFFF 0032 After Instruction A AR1 FF FFFF FFFF 0033 If the content of accumulator A is less than or equal to 0, AR1 is modified before the execution of the addition instruction. 4-204 Assembly Language Instructions SPRU179C Exclusive OR With Accumulator Syntax src = src ^ Smem src ^= Smem dst = src ^ #lk [ << SHFT ] dst ^= #lk [ << SHFT ] dst = src ^ #lk << 16 dst ^= #lk << 16 dst = dst ^ src [ << SHIFT ] dst ^= src [ << SHIFT ] 1: 2: 3: 4: Operands src, dst: A (accumulator A) B (accumulator B) Smem: Single data-memory operand 0 v SHFT v 15 –16 v SHIFT v 15 0 v lk v 65 535 Opcode 1: 15 0 14 0 13 0 12 1 11 1 10 1 9 0 8 S 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 6 1 5 0 4 1 3 S 2 H 1 F 0 T 5 1 4 0 3 0 2 1 1 0 0 1 5 0 4 S 3 H 2 I 1 F 0 T 2: 16-bit constant 3: 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 0 6 1 16-bit constant 4: 15 1 14 1 13 1 12 1 11 0 10 0 9 S 8 D 7 1 6 1 (Smem) XOR (src) ³ src lk << SHFT XOR (src) ³ dst lk << 16 XOR (src) ³ dst (src) << SHIFT XOR (dst) ³ dst Execution 1: 2: 3: 4: Status Bits None Description This instruction executes an exclusive OR of the 16-bit single data-memory operand Smem (shifted as indicated in the instruction) with the content of the selected accumulator and stores the result in dst or src, as specified. For a left shift, the low-order bits are cleared and the high-order bits are not sign extended. For a right shift, the sign is not extended. SPRU179C Assembly Language Instructions 4-205 Exclusive OR With Accumulator Words Syntaxes 1 and 4: 1 word Syntaxes 2 and 3: 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles Syntaxes 1 and 4: 1 cycle Syntaxes 2 and 3: 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Syntax 1: Class 3A (see page 3-6) Syntax 1: Class 3B (see page 3-8) Syntaxes 2 and 3: Class 2 (see page 3-5) Syntax 4: Class 1 (see page 3-3) Example 1 A = *AR3+ ^ A Before Instruction A 00 00FF 1200 AR3 After Instruction A 00 00FF 0700 0100 AR3 0101 1500 0100h 1500 Data Memory 0100h Example 2 B = B ^ A << +3 Before Instruction After Instruction A A 00 0000 1200 B 4-206 00 0000 1200 00 0000 1800 B 00 0000 8800 Assembly Language Instructions SPRU179C Exclusive OR Memory With Constant Syntax Smem = Smem ^ #lk Smem ^= #lk Operands Smem: Single data-memory operand 0 v lk v 65 535 Opcode 15 0 14 1 13 1 12 0 11 1 10 0 9 1 8 0 7 I 6 A 5 A 4 A 3 A 2 A 1 A 0 A Execution lk XOR (Smem) ³ Smem Status Bits None Description This instruction executes an exclusive OR of the content of a data-memory location Smem with a 16-bit constant lk. The result is written to Smem. Note: This instruction is not repeatable. Words 2 words Add 1 word when using long-offset indirect addressing or absolute addressing with an Smem. Cycles 2 cycles Add 1 cycle when using long-offset indirect addressing or absolute addressing with an Smem. Classes Class 18A (see page 3-41) Class 18B (see page 3-41) Example *AR4– = *AR4– ^ #0404h Before Instruction AR4 After Instruction 0100 AR4 00FF 4444 0100h 4040 Data Memory 0100h SPRU179C Assembly Language Instructions 4-207 Appendix A Appendix A Condition Codes This appendix lists the conditions for conditional instructions (Table A–1) and the combination of conditions that can be tested (Table A–2). Conditional instructions can test conditions individually or in combination with other conditions. You can combine conditions from only one group as follows: Group1: You can select up to two conditions. Each of these conditions must be from a different category (category A or B); you cannot have two conditions from the same category. For example, you can test EQ and OV at the same time but you cannot test GT and NEQ at the same time. The accumulator must be the same for both conditions; you cannot test conditions for both accumulators with the same instruction. For example, you can test AGT and AOV at the same time, but you cannot test AGT and BOV at the same time. Group 2: You can select up to three conditions. Each of these conditions must be from a different category (category A, B, or C); you cannot have two conditions from the same category. For example, you can test TC, C, and BIO at the same time but you cannot test NTC, C, and NC at the same time. A-1 A-2 Condition Codes SPRU179C ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á † Cannot be used with conditional store instructions Operand Condition Description AEQ A=0 Accumulator A equal to 0 BEQ B=0 Accumulator B equal to 0 ANEQ A00 Accumulator A not equal to 0 BNEQ B00 Accumulator B not equal to 0 ALT A<0 Accumulator A less than 0 BLT B<0 Accumulator B less than 0 ALEQ Av0 Accumulator A less than or equal to 0 BLEQ Bv0 Accumulator B less than or equal to 0 AGT A>0 Accumulator A greater than 0 BGT B>0 Accumulator B greater than 0 AGEQ Aw0 Accumulator A greater than or equal to 0 BGEQ Bw0 Accumulator B greater than or equal to 0 AOV† AOV = 1 Accumulator A overflow detected BOV† BOV = 1 Accumulator B overflow detected ANOV† AOV = 0 No accumulator A overflow detected BNOV† BOV = 0 No accumulator B overflow detected C† C=1 ALU carry set to 1 NC† C=0 ALU carry clear to 0 TC† TC = 1 Test/Control flag set to 1 NTC† TC = 0 Test/Control flag cleared to 0 BIO† BIO low BIO signal is low NBIO† BIO high BIO signal is high UNC† none Unconditional operation Table A–1. Conditions for Conditional Instructions Conditions for Conditional Instructions Groupings of Conditions Table A–2. Groupings of Conditions Group 1 Group 2 Category A Category B Category A Category B Category C EQ OV TC C BIO NEQ NOV NTC NC NBIO LT LEQ GT GEQ SPRU179C Condition Codes A-3 Appendix B Appendix A CPU Status and Control Registers This appendix shows the bit fields of the TMS320C54x™ CPU status and control registers. The C54x™ DSP has three status and control registers: - Status register 0 (ST0) - Status register 1 (ST1) - Processor mode status register (PMST) ST0 and ST1 contain the status of various conditions and modes; PMST contains memory-setup status and control information. Because these registers are memory-mapped, they can be stored into and loaded from data memory; the status of the processor can be saved and restored for subroutines and interrupt service routines (ISRs). Table B–1 defines terms used in identifying the register fields. Table B–1. Register Field Terms and Definitions Term Definition ARP Auxiliary register pointer ASM Accumulator shift mode AVIS Address visibility mode BRAF Block repeat active flag C Carry CLKOFF CLOCKOUT off CMPT Compatibility mode CPL Compiler mode C16 Dual 16-bit/double-precision arithmetic mode DP Data page pointer DROM Data ROM FRCT Fractional mode B-1 CPU Status and Control Registers Table B–1. Register Field Terms and Definitions (Continued) Term Definition HM Hold mode INTM Interrupt mode IPTR Interrupt vector pointer MP/MC Microprocessor/microcomputer OVA Overflow flag A OVB Overflow flag B OVLY RAM overlay OVM Overflow mode SMUL Saturation on multiplication SST Saturation on store SXM Sign-extension mode TC Test/control flag XF External flag status Figure B–1. Processor Mode Status Register (PMST) 15–7 6 5 4 3 2 1 0 IPTR MP/MC OVLY AVIS DROM CLKOFF † SMUL† SST † † These bits are only supported on C54x devices with revision A or later, or on C54x devices numbered C548 or greater. You may also refer to the device-specific data sheet to determine if these bits are supported. Figure B–2. Status Register 0 (ST0) 15–13 12 11 10 9 8–0 ARP TC C OVA OVB DP Figure B–3. Status Register 1 (ST1) 15 14 13 12 11 10 9 8 7 6 5 4–0 BRAF CPL XF HM INTM 0 OVM SXM C16 FRCT CMPT ASM B-2 CPU Status and Control Registers SPRU179C Appendix C Appendix A Glossary A A: See accumulator A. accumulator: A register that stores the results of an operation and provides an input for subsequent arithmetic logic unit (ALU) operations. accumulator A: One of two 40-bit registers that store the result of an operation and provide an input for subsequent arithmetic logic unit (ALU) operations. accumulator B: One of two 40-bit registers that store the result of an operation and provide an input for subsequent arithmetic logic unit (ALU) operations. accumulator shift mode bits (ASM): A 5-bit field in ST1 that specifies a shift value (from –16 to 15) that is used to shift an accumulator value when executing certain instructions, such as instructions with parallel loads and stores. address: The location of a word in memory. address visibility mode bit (AVIS): A bit in PMST that determines whether or not the internal program address appears on the device’s external address bus pins. addressing mode: The method by which an instruction calculates the location of an object in memory. AG: Accumulator guard bits. An 8-bit register that contains bits 39–32 (the guard bits) of an accumulator. Both accumulator A and accumulator B have guards bits. AH: Accumulator A high word. Bits 31–16 of accumulator A. AL: Accumulator A low word. Bits15–0 of accumulator A. C-1 Glossary ALU: Arithmetic logic unit. The part of the CPU that performs arithmetic and logic operations. AR0–AR7: See auxiliary registers. ARAU: See auxiliary register arithmetic unit. ARP: See auxiliary register pointer. ASM: See accumulator shift mode bits. auxiliary register arithmetic unit (ARAU): An unsigned, 16-bit arithmetic logic unit (ALU) used to calculate indirect addresses using auxiliary registers. auxiliary register file: The area in data memory containing the eight 16-bit auxiliary registers. See also auxiliary registers. auxiliary register pointer (ARP): A 3-bit field in ST0 used as a pointer to the currently-selected auxiliary register, when the device is operating in ’C5x/’C2xx compatibility mode. auxiliary registers (AR0–AR7): Eight 16-bit registers that are used as pointers to an address within data space. These registers are operated on by the auxiliary register arithmetic units (ARAUs) and are selected by the auxiliary register pointer (ARP). See also auxiliary register arithmetic unit. AVIS: See address visibility mode bit. B B: See accumulator B. barrel shifter: A unit that rotates bits in a word. BG: Accumulator B guard bits. An 8-bit register that contains bits 39–32 (the guard bits) of accumulator B. BH: Accumulator B high word. Bits 31–16 of accumulator B. BL: Accumulator B low word. Bits 15–0 of accumulator B. block-repeat active flag (BRAF): A 1-bit flag in ST1 that indicates whether or not a block repeat is currently active. block-repeat counter (BRC): A 16-bit register that specifies the number of times a block of code is to be repeated when a block repeat is performed. C-2 Glossary SPRU179C Glossary block-repeat end address register (REA): A 16-bit memory-mapped register containing the end address of a code segment being repeated. block-repeat start address register (RSA): A 16-bit memory-mapped register containing the start address of a code segment being repeated. boot: The process of loading a program into program memory. boot loader: A built-in segment of code that transfers code from an external source to program memory at power-up. BRC: See block-repeat counter. butterfly: A kernel function for computing an N-point fast Fourier transform (FFT), where N is a power of 2. The combinational pattern of inputs resembles butterfly wings. C C16: A bit in ST1 that determines whether the ALU operates in dual 16-bit mode or in double-precision mode. CAB: C address bus. A bus that carries addresses needed for accessing data memory. carry bit (C): A bit used by the ALU in extended arithmetic operations and accumulator shifts and rotates. The carry bit can be tested by conditional instructions. CB: C bus. A bus that carries operands that are read from data memory. CMPT: See compatibility mode bit. code: A set of instructions written to perform a task. cold boot: The process of loading a program into program memory at power-up. compatibility mode bit (CMPT): A bit in ST1 that determines whether or not the auxiliary register pointer (ARP) is used to select an auxiliary register in single indirect addressing mode. compiler mode bit (CPL): A bit in ST1 that determines whether the CPU uses the data page pointer or the stack pointer to generate data memory addresses in direct addressing mode. CPL: See compiler mode bit. SPRU179C Glossary C-3 Glossary D DAB: D address bus. A bus that carries addresses needed for accessing data memory. DAB address register (DAR): A register that holds the address to be put on the DAB to address data memory for reads via the DB. DAGEN: See data address generation logic. DAR: See DAB address register. DARAM: Dual-access RAM. Memory that can be accessed twice in the same clock cycle. data address bus: A group of connections used to route data memory addresses. The C54x DSP has three 16-bit buses that carry data memory addresses: CAB, DAB, and EAB. data address generation logic (DAGEN): Logic circuitry that generates the addresses for data memory reads and writes. See also program address generation logic. data bus: A group of connections used to route data. The C54x DSP has three 16-bit data buses: CB, DB, and EB. data memory: A memory region used for storing and manipulating data. Addresses 00h–1Fh of data memory contain CPU registers. Addresses 20h–5Fh of data memory contain peripheral registers. data page pointer (DP): A 9-bit field in ST0 that specifies which of 512 128-word pages is currently selected for direct address generation. DP provides the nine MSBs of the data-memory address; the data memory address provides the lower seven bits. See also direct memory address. data ROM bit (DROM): A bit in processor mode status register (PMST) that determines whether part of the on-chip ROM is mapped into program space. DB: D bus. A bus that carries operands that are read from data memory. direct memory address (dma, DMA): The seven LSBs of a directaddressed instruction that are concatenated with the data page pointer (DP) to generate the entire data memory address. See also data page pointer. dma: See direct memory address. DP: See data page pointer. DROM: See data ROM bit. C-4 Glossary SPRU179C Glossary E EAB address register (EAR): A register that holds the address to be put on the EAB to address data memory for reads via the EB. EAR: See EAB address register. EB: E bus. A bus that carries data to be written to memory. exponent (EXP) encoder: A hardware device that computes the exponent value of the accumulator. F fast return register (RTN): A 16-bit register used to hold the return address for the fast return from interrupt instruction. fractional mode bit (FRCT): A bit in status register ST1 that determines whether or not the multiplier output is left-shifted by one bit. FRCT: See fractional mode bit. H HM: See hold mode bit. hold mode bit (HM): A bit in status register ST1 that determines whether the CPU enters the hold state in normal mode or concurrent mode. I IFR: See interrupt flag register. IMR: See interrupt mask register. instruction register (IR): A 16-bit register used to hold a fetched instruction. interrupt: A condition caused by internal hardware, an event external to the CPU, or by a previously executed instruction that forces the current program to be suspended and causes the processor to execute an interrupt service routine corresponding to the interrupt. interrupt flag register (IFR): A 16-bit memory-mapped register used to identify and clear active interrupts. SPRU179C Glossary C-5 Glossary interrupt mask register (IMR): A 16-bit memory-mapped register used to enable or disable external and internal interrupts. A 1 written to any IMR bit position enables the corresponding interrupt (when INTM = 0). interrupt mode bit (INTM): A bit in status register ST1 that globally masks or enables all interrupts. interrupt service routine (ISR): A module of code that is executed in response to a hardware or software interrupt. INTM: See interrupt mode bit. IPTR: Interrupt vector pointer. A 9-bit field in the processor mode status register (PMST) that points to the 128-word page where interrupt vectors reside. IR: See instruction register. ISR: See interrupt service routine. L latency: The delay between when a condition occurs and when the device reacts to the condition. Also, in a pipeline, the delay between the execution of two instructions that is necessary to ensure that the values used by the second instruction are correct. LSB: Least significant bit. The lowest order bit in a word. M memory-mapped register (MMR): The ’54x processor registers mapped into page 0 of the data memory space. microcomputer mode: A mode in which the on-chip ROM is enabled and addressable. microprocessor mode: A mode in which the on-chip ROM is disabled. micro stack: A stack that provides temporary storage for the address of the next instruction to be fetched when the program address generation logic is used to generate sequential addresses in data space. MP/MC bit: A bit in the processor mode status register (PMST) that indicates whether the processor is operating in microprocessor or microcomputer mode. See also microcomputer mode; microprocessor mode. MSB: Most significant bit. The highest order bit in a word. C-6 Glossary SPRU179C Glossary O OVA: Overflow flag A. A bit in status register ST0 that indicates the overflow condition of accumulator A. OVB: Overflow flag B. A bit status register ST0 that indicates the overflow condition of accumulator B. overflow: A condition in which the result of an arithmetic operation exceeds the capacity of the register used to hold that result. overflow flag (OVA, OVB): A flag that indicates whether or not an arithmetic operation has exceeded the capacity of the corresponding accumulator. See also OVA and OVB. overflow mode bit (OVM): A bit in status register ST1 that specifies how the ALU handles an overflow after an operation. OVLY: See RAM overlay bit. OVM: See overflow mode bit. P PAB: Program address bus. A 16-bit bus that provides the address for program memory reads and writes. PAGEN: See program address generation logic. PAR: See program address register. PB: Program bus. A bus that carries the instruction code and immediate operands from program memory. PC: See program counter. pipeline: A method of executing instructions in an assembly-line fashion. pmad: Program-memory address. A 16-bit immediate program-memory address. PMST: See processor mode status register. pop: Action of removing a word from a stack. processor mode status register (PMST): A 16-bit status register that controls the memory configuration of the device. See also ST0; ST1. SPRU179C Glossary C-7 Glossary program address generation logic (PAGEN): Logic circuitry that generates the address for program memory reads and writes, and the address for data memory in instructions that require two data operands. This circuitry can generate one address per machine cycle. See also data address generation logic. program address register (PAR): A register that holds the address to be put on the PAB to address memory for reads via the PB. program controller: Logic circuitry that decodes instructions, manages the pipeline, stores status of operations, and decodes conditional operations. program counter (PC): A 16-bit register that indicates the location of the next instruction to be executed. program counter extension register (XPC): A register that contains the upper 7 bits of the current program memory address. program data bus (PB): A bus that carries the instruction code and immediate operands from program memory. program memory: A memory region used for storing and executing programs. push: Action of placing a word onto a stack. R RAM overlay bit (OVLY): A bit in the processor mode status register PMST that determines whether or not on-chip dual-access RAM is mapped into the program/data space. RC: See repeat counter. REA: See block-repeat end address. register: A group of bits used for temporarily holding data or for controlling or specifying the status of a device. repeat counter (RC): A 16-bit register used to specify the number of times a single instruction is executed. reset: A means of bringing the CPU to a known state by setting the registers and control bits to predetermined values and signaling execution to start at a specified address. RSA: See block-repeat start address. RTN: See fast return register. C-8 Glossary SPRU179C Glossary S SARAM: Single-access RAM. Memory that only can be read from or written during one clock cycle. shifter: A hardware unit that shifts bits in a word to the left or to the right. sign-control logic: Circuitry used to extend data bits (signed/unsigned) to match the input data format of the multiplier, ALU, and shifter. sign extension: An operation that fills the high order bits of a number with the sign bit. sign-extension mode bit (SXM): A bit in status register ST1 that enables sign extension in CPU operations. SINT: See software interrupt. software interrupt: An interrupt caused by the execution of a software interrupt instruction. SP: See stack pointer. ST0: Status register 0. A 16-bit register that contains C54x CPU status and control bits. See also PMST; ST1. ST1: Status register 1. A16-bit register that contains C54x CPU status and control bits. See also PMST; ST0. stack: A block of memory used for storing return addresses for subroutines and interrupt service routines and for storing data. stack pointer (SP): A register that always points to the last element pushed onto the stack. SXM: See sign-extension mode bit. T TC: See test/control flag bit. temporary register (T): A 16-bit register that holds one of the operands for multiply and store instructions, the dynamic shift count for the add and subtract instructions, or the dynamic bit position for the bit test instructions. test/control flag bit (TC): operations. A bit in status register ST0 that is affected by test transition register (TRN): A 16-bit register that holds the transition decision for the path to new metrics to perform the Viterbi algorithm. SPRU179C Glossary C-9 Glossary W warm boot: The process by which the processor transfers control to the entry address of a previously-loaded program. X XF: XF status flag. A bit in status register ST1 that indicates the status of the XF pin. XPC: See program counter extension register. Z ZA: Zero detect bit A. A signal that indicates when accumulator A contains a 0. ZB: Zero detect bit B. A signal that indicates when accumulator B contains a 0. zero detect: See ZA and ZB. zero fill: A method of filling the low- or high-order bits with zeros when loading a 16-bit number into a 32-bit field. C-10 Glossary SPRU179C Index Index A abdst 4-2 accumulator A C-1 accumulator A high word (AH) C-1 accumulator A low word (AL) C-1 accumulator B C-1 accumulator B guard bits (BG) C-2 accumulator B high word (BH) C-2 accumulator B low word (BL) C-2 accumulator guard bits (AG) C-1 accumulator shift mode (ASM) C-1 accumulators C-1 add instructions 2-2 to 2-3 address C-1 address visibility mode bit (AVIS) C-1 addressing mode C-1 AND instructions 2-9 application-specific instructions 2-8 AR0–AR7. See auxiliary registers ARAU. See auxiliary register arithmetic unit arithmetic logic unit (ALU) C-2 arithmetic operation instructions 2-2 add instructions 2-2 to 2-3 application-specific instructions 2-8 double (32-bit operand) instructions 2-7 multiply instructions 2-4 multiply-accumulate instructions 2-5 to 2-6 multiply-subtract instructions 2-5 to 2-6 subtract instructions 2-3 to 2-4 ARP. See auxiliary register pointer ASM. See accumulator shift mode bits assembly language instructions 4-1 auxiliary register arithmetic unit (ARAU) auxiliary register file C-2 auxiliary register pointer (ARP) C-2 auxiliary registers (AR0–AR7) C-2 AVIS. See address visibility mode bit C-2 B B. See accumulator B barrel shifter C-2 block-repeat active flag (BRAF) C-2 block-repeat counter (BRC) C-2 block-repeat end address register (REA) C-3 block-repeat start address register (RSA) C-3 boot C-3 boot loader C-3 branch instructions 2-12 BRC. See block-repeat counter butterfly C-3 C C address bus (CAB) C-3 C bus (CB), definition C-3 C16 C-3 call instructions 2-13 carry bit (C), definition C-3 cmps 4-35 CMPT. See compatibility mode bit code, definition C-3 cold boot, definition C-3 compatibility mode bit (CMPT), definition compiler mode bit (CPL), definition C-3 conditional instructions conditions A-2 grouping of conditions A-3 C-3 Index-1 Index conditional store instructions 2-18 H CPL. See compiler mode bit HM. See hold mode bit hold mode bit (HM), definition D D address bus (DAB), definition D bus (DB), definition I C-4 C-4 DAB address register (DAR), definition C-4 DAGEN. See data address generation logic DAR. See DAB address register DARAM 3-1 data address bus, definition C-4 data address generation logic (DAGEN), definition C-4 data bus, definition C-4 data memory, definition C-4 data page pointer (DP), definition C-4 data ROM bit (DROM), definition C-4 delay 4-41 direct memory address, definition C-4 double (32-bit operand) instructions 2-7 DP. See data page pointer DROM 3-1 See also data ROM bit dual-access RAM (DARAM), definition C-4 E E bus (EB), definition C-5 EAB address register (EAR), definition C-5 EAR. See EAB address register EXP encoder, definition C-5 exponent encoder, definition C-5 F fast return register (RTN), definition firs C-5 4-60 fractional mode bit (FRCT), definition FRCT. See fractional mode bit Index-2 C-5 C-5 idle 4-64 IFR. See interrupt flag register IMR. See interrupt mask register instruction cycles, assumptions 3-2 instruction register (IR), definition C-5 instruction set abbreviations 1-2 classes 3-3 to 3-74 cycle tables 3-3 to 3-74 example description 1-9 notations 1-7 opcode abbreviations 1-5 opcode symbols 1-5 operators 1-8 symbols 1-2 instruction set summary add instructions 2-2 to 2-3 AND instructions 2-9 application-specific instructions 2-8 branch instructions 2-12 call instructions 2-13 conditional store instructions 2-18 double (32-bit operand) instructions 2-7 interrupt instructions 2-13 load instructions 2-16 to 2-17 miscellaneous load-type and store-type instructions 2-21 miscellaneous program control instructions 2-15 multiply instructions 2-4 multiply-accumulate instructions 2-5 to 2-6 multiply-subtract instructions 2-5 to 2-6 OR instructions 2-10 parallel load and multiply instructions 2-19 parallel load and store instructions 2-19 parallel store and add/subtract instructions 2-19 parallel store and multiply instructions 2-20 repeat instructions 2-14 return instructions 2-14 shift instructions 2-11 stack-manipulating instructions 2-15 store instructions 2-18 Index subtract instructions 2-3–2-4 test instructions 2-11 XOR instructions 2-10 int 4-66 interrupt, definition C-5 interrupt flag register (IFR), definition C-6 interrupt instructions 2-13 interrupt mask register (IMR), definition C-6 interrupt mode bit (INTM), definition C-6 interrupt service routine (ISR), definition C-6 interrupt vector pointer (IPTR), definition C-6 INTM. See interrupt mode bit IR. See instruction register ISR. See interrupt service routine L latency, definition C-6 least significant bit (LSB), definition C-6 lms 4-81 load and store operation instructions 2-16 conditional store instructions 2-18 load instructions 2-16 to 2-17 miscellaneous instructions 2-21 parallel load and multiply instructions 2-19 parallel load and store instructions 2-19 parallel store and add/subtract instructions 2-19 parallel store and multiply instructions 2-20 store instructions 2-18 load instructions 2-16 to 2-17 logical operation instructions 2-9 AND instructions 2-9 OR instructions 2-10 shift instructions 2-11 test instructions 2-11 XOR instructions 2-10 M macd 4-89 macp 4-91 mar 4-94 max 4-101 memory-mapped register (MMR), definition micro stack, definition C-6 microcomputer mode, definition C-6 C-6 microprocessor mode, definition C-6 min 4-102 miscellaneous load-type and store-type instructions 2-21 miscellaneous program control instructions 2-15 MMR 3-1 most significant bit (MSB), definition C-6 MP/MC bit, definition C-6 multi-cycle instructions, transformed to single-cycle 2-22 multiply instructions 2-4 multiply-accumulate instructions 2-5 to 2-6 multiply-subtract instructions 2-5 to 2-6 N negation 4-121 nonrepeatable instructions nop 4-123 2-23 O OR instructions 2-10 OVA. See overflow flag A OVB. See overflow flag B overflow, definition C-7 overflow flag, definition C-7 overflow flag A (OVA), definition C-7 overflow flag B (OVB), definition C-7 overflow mode bit (OVM), definition C-7 OVLY. See RAM overlay bit OVM. See overflow mode bit P PAGEN. See program address generation logic PAR. See program address register parallel load and multiply instructions 2-19 parallel load and store instructions 2-19 parallel store and add/subtract instructions 2-19 parallel store and multiply instructions 2-20 PC. See program counter pipeline, definition C-7 pmad, definition C-7 PMST. See processor mode status register Index-3 Index poly 4-128 pop, definition C-7 processor mode status register (PMST) definition C-7 figure B-2 program address bus (PAB), definition C-7 program address generation logic (PAGEN), definition C-8 program address register (PAR), definition C-8 program bus (PB), definition C-7 program control operation instructions 2-12 branch instructions 2-12 call instructions 2-13 interrupt instructions 2-13 miscellaneous instructions 2-15 repeat instructions 2-14 return instructions 2-14 stack-manipulating instructions 2-15 program controller, definition C-8 program counter (PC), definition C-8 program counter extension (XPC), definition C-8 program data bus (PB), definition C-8 program memory, definition C-8 program memory address (pmad), definition C-7 PROM 3-1 push, definition C-8 R RAM overlay bit (OVLY), definition C-8 RC. See repeat counter REA. See block-repeat end address register, definition C-8 repeat counter (RC), definition C-8 repeat instructions 2-14 repeat operation 2-22 handling multicycle instructions 2-22 nonrepeatable instructions 2-23 reset 4-140 definition C-8 return instructions 2-14 ROM 3-1 RSA. See block-repeat start address RTN. See fast return register Index-4 S SARAM 3-1 saturate 4-156 shift instructions 2-11 shiftc 4-159 shifter, definition C-9 sign control logic, definition C-9 sign extension, definition C-9 sign-extension mode bit (SXM), definition C-9 single-access RAM (SARAM), definition C-9 SINT. See software interrupt software interrupt, definition C-9 SP. See stack pointer sqdst 4-162 ST0, definition. See status register 0 ST1, definition. See status register 1 stack, definition C-9 stack pointer (SP), definition C-9 stack-manipulating instructions 2-15 status register 0 (ST0) definition. See PMST, ST1 figure B-2 status register 1 (ST1) definition. See PMST, ST0 figure B-2 store instructions 2-18 subc 4-196 subtract instructions 2-3 to 2-4 SXM. See sign-extension mode bit T TC. See test/control flag bit temporary register (T), definition C-9 test instructions 2-11 test/control flag bit (TC), definition C-9 transition register (TRN), definition C-9 trap 4-199 W warm boot, definition C-10 Index X Z XF status flag (XF), definition XOR instructions C-10 2-10 XPC. See program counter extension register zero detect. See zero detect bit A; zero detect bit B zero detect bit A (ZA), definition C-10 zero detect bit B (ZB), definition C-10 zero fill, definition C-10 Index-5 ...
View Full Document

This note was uploaded on 11/06/2010 for the course EE 113 taught by Professor Walker during the Spring '08 term at UCLA.

Ask a homework question - tutors are online