113D_1_EE113D_CR4_AC01

113D_1_EE113D_CR4_AC01 - ( @ 1998, Dr. M. Wer ter...

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Unformatted text preview: ( @ 1998, Dr. M. Wer ter ELECTRICAL ENGINEERING 113L D igital Signal Processing Laboratory L e ct u r e 3: Analog Interface Circuit Introduction In general, t o im plement real-time signal processing on a "DSP chip, there needs to be a procedure for real-world (analog) data to be provided in digital format to th e DSP chip, and for t he DSP 's output results to be transferred into the outside real world. Naturally, this requires the use of analog-to-digital (A/D) and digital- to-anal og (D/ A) conversion circuits, which enable t he DSP to deal with digital information for which it has been des igned. The associated timing circuitry and the DSP instructions required to coordinate these activities form th e I/ O processing s ub-s ystem of a DSP sy ste m. All DSP syst ems have a similar sub-system which coordinates inp u t/output procedures. On the DSKplus board, the A/ D , D/A procedures, timing and synchronizati on , and some anal og pre-pro cessin g are all h andl ed by the TLC320ACOl single-supply an alog interface circuit (AIC) and its supportin g circuitry. All of t hese are c ontrolled by software directed from the TMS3 20C542 main-bo ard DSP chip. Thus, input / ou t put procedures simplify to "initialization" and "I /O han dling" subroutines which the us er has t o progr am and exec u te on the host DSP. In this experiment , we will invest igate in detail two sim ple progr ams which implement the proced ures ment ioned above. The TLC320ACO I an alog interface circuit The TLC320ACOI an alog int er face circuit (AIC) is an audio-band processor that provides an anal og-to-di git al and d igital-t o-an alog input/output interface system on a single CMOS chip . A fun cti onal Block diagram of this chip is shown in figure 1.2. 1.2 Functional Block D iagram ..ON OUT -'--4 - - --< I - ' FCO FC1 DAC Voo DAC GND 0GT1. Yoo Th is analog int erface circuit (AIC) contains a 14-bit-resolution analog-to-digital converter (ADC), a 14-bit- resolution digi tal-to-an alog converter (DAC), a band-pass anti-aliasing input filter (containing a cascade of a low-pass and highpass filter), a low-pass o utp ut- rec onstruction filter , a (sin x)/x output compensator, and a serial port for data and control transfer. The internal circuit configur at ion and performance parameters are determined by readi ng control in format ion into eight available data registers. T he register data sets up the device for a given mo de of operation and application . The major functions of the 'ACOI ar e: I) To convert (analog) audio-signal dat a to digital format by the ADC channel 2) To provide the int erface and cont rol logic to transfer data between its serial input and output terminals and a digital signal processor (DSP) or microporcessor 3) To convert received digital data back to an (analog) audio signal t hr ough the DAC channel The anti-aliasing input low-pass filter is a switched-capacitor filter with a sixt h-order eIliptic ch arac t eristic. The high-pass filter is a single pole filter to preserve low-frequency response as the low-pass filter cutoff is adjusted . There is a t hird-order continuous-time (analog) filter that precedes t he switched-capacitor filter to elimin ate any aliasi ng 1 67 ( ca used by th e filter clock signal. Th e out pu t-reco nstru ction swit che d-ca pacitor filter is a six t h-or de r elli pt ic transitional low-pass filter followed by a second- order (sin x )/x correct ion filt er. T his filter is followed by a third -or der conti nuous-time (analog ) filter to elimin ate images of th e filter clock signal. Th e 'AC01 consis ts of two signal -p rocessing channels, an AD C chan nel and a DAC chan nel, an d the asso ciate d digital cont rol. The two channels operate synchronously; t h at is, dat a reception at the DAC channel and dat a t ran smission from th e ADC ch an nel occur during t he same time interval. T he data trans fer is in 2s-complement num ber re p resentat ion format. T here are t hr ee basic modes of operation available: 1) Th e stan d-alone an alog-int erface mod e 2) The master-slave mod e 3) Th e linear-cod ec mod e In the st and-alone mode, the ' AC0 1 gener a tes t he shift clock and frame synch ronization for the data transfe rs and is t he on ly AIC used. The master-s la ve mo de has one' AC01 as the master that generates the master-shift clock and frame syn chr onization ; the rem ai ning AICs are slaves t o thes e signals. In th e linear-codec mode , th e shift clock and the frame-synchron ization sign als are externally genera ted and the timing can be any of the st an d ard codec-timing pa tterns . T yp ical applications for this device include mode ms , speech processing, analog interface for DSPs, in dus t ri al-process control, aco ust ic- signal pro cessing, s pect ral analysis, data acq uisition , and instrum entation recorders. Cont rol Flow Diagram 5 . 184 MHz 10.368 MH z ( MC1. K DIvlde by 4 SCLK 1.296 MHz 2.592 MH z fCU( (Iow-pau "he< ond (s in - )Ix "he< dod'! Figure 1 -1. Control Flow Diagram There are 9 data registers that are used as follows: Re gister 0: the No-Op register. The 0 address allows phase adjustments to be made without reprogram m ing a data register . Register 1: The A regist er controls the count of t he A cou nter (t o be discussed in a minute) Reg ister 2: The B register controls the count of the B counter (to be discussed in a minute) Register 3: T he A' register cont rols the phase adjustment of th e sampli ng p eri od. Th e adj ust me nt is equal to th e register value multiplied by t he in p ut master period . Regis ter 4: The amplifier gain register controls t he gain of the in put , o utput, and monitor amplifiers. Register 5: The analog configuration regist er controls the addit ion/ deletion of the high-pass filter for the ADC signal pat h , the enable/disable of the analog loopback , the selection of regular inpu ts or auxiliary inputs or t he sum of t hese. Regis ter 6: T he di git al configur at ion register controls: free-run, fr am e synchronization , software reset and software power down. Register 7: T he frame-sy nchron izat ion delay regis te r controls t he t ime delay between t he master-device fr ame sync 2 68 ( and slave-device frame sync. Registe r 8: T he fr ame- synchroniz at ion numb er regis ter informs t he mast er device of t he number of slaves t h at ar e connec te d . ADC Signal C h ann el To produce excellent common-mode rejection of unwanted signals , th e analog signal is pro cessed differentially unti l it is converted to digital data. The signal is amplified by t he input amplifi er at one of thr ee software-selectab le gains (ty pical ly 0 dB , 6 dB, or 12 dB ). T he amplifier output is filtered and applied to t he ADC inp ut . T he ADC converts t he signal into di screte d igi tal words in 2s-complement nu mber represent ation form at corresponding to t he analog-signal value at t he sampling time. T hese 16-bit digital words , represent ing samp led values of t he analog input signal, are clocked out of the seri al por t (DOUT), one word for each primary commun ication interval . During secondar y co mmuni cati ons , t he data previously progr am m ed into th e register can be read out with th e appro priate register address an d wi th the read bit set t o 1. When a reg ister re ad is not requ ested , all 16 bi ts are O. DAC Sig n al Chan nel DIN, the di gital data input terminals, receives the 16-bit serial data (2s complement form at ) from the host during the primary com munications interval and latches th e data on th e seventeenth rising edge of t h e system clock (SCLK ). The data are co nver t ed to an anlog voltage by th e DA C wit h a s am ple and hold, and then through the (sin x)/x correction circuit and a smoothing filter. An out put buffer wit h three software-programm able gains (0 dB, -6 dB , an d -12 dB), as shown in Register 4, drives the differential outputs O UT + and OUT -. During secondar y communications , t he configuration program data are read into the device co n tro l registers. t+-I ~ ((B sctx JliUi:~~ AA 1 I I I I I k - 16 SCLKs ----+l I I J.t-.-- 16 SCL Ks Fnme-Sync In_ -+t regtste<Y2J FCl.J( PHIod.t ----+j I ~ fra .....s ync In ' ....a' -+j FS DOUT -k ADC~~ 'j~1I I ---.:r I I -r r I I K _._~~c>- t The _ oeccndoIy _ ayncIs !he lima oquoI lo _dod< (FCU<l period nUlfPied by!he 1k'egIs1at ~ _ by _. lbo _ kll ..... 1s rounded 10 Iha . - . . . _ dock. The oeccndoIyhtM-sync signal _ '""" IOgh 10 _on !he ' - _ dock ~ _ an... (B n>gIsIen'Z) _ dod< periods. ~N ~ DAC _+~ - ' !he primaIy _ ~e-d _ =~ R gure 2-1. Functlonal Sequence fo r PrImary and Secondary Communi cation 'ACO! Master-Slave operation After initial setup and the master and slave frame syncs are separ a ted , when second ary comm unication is needed for a slave device, a 11 must be placed in the 2 LSB of each primary dat a word for all devices in the syst em , master an d slave, by the host processor. In other words , all AICs must receive secondary frame requests. The host must keep track of wh et her the mas ter or a slave is th en bei ng addressed and also the number of slav e devices. T h e mas t er al w ays outputs a 00 in t he last 2 bits of the DOUT word, and a slave always o utpu ts a 1 in t he LSB of t he DOUT word . The means that only the 14 MSB can be used for data . Master and Stand- A lo ne Operat ing Frequencies T he sampling (conversion) freq uency is derived from the m aste r-clock (MCLK) input by Fs The system cloc k (S CL K) is given by = MCLK 2.A .B SCLK = MC LK 4 3 69 ( Filt er Band widths The filter clock (FCLK) is an intern al clock signal for the band-pass filter, which is used for the B coun ter: FCLK = M CLK 2.A given by the equation 80.A The low-pass (LP) filt er has a - 3d B corner frequency F LP - FLP _ FCLK _ MCLK 40 The high-pass (HP) filter has a - 3dB corner frequency FHP given by the eq uati on F _ Fs _ MCLK HP - 200 - 400.A .B Ex amples: Let MCLK = 10.368 MHz t hen A= A= A= A= A= A= A= A= A= A= A= A= 36 36 36 36 18 18 18 18 12 12 12 12 ( FLP FLP FLP FLP FLP FLP FLP FLP FLP FLP FLP FLP = = = = = = = = 3.6 kHz 3.6 kHz 3.6 kHz 3.6 kHz 7.2 kHz 7.2 kHz 7.2 kHz 7.2 kHz =10.8 kHz =10.8 kHz =10 .8 kHz =10 .8 kHz B = 20 B = 18 B = 15 B = 10 B = 20 B = 18 B = 15 B = 10 B = 20 B = 18 B = 15 B=lO Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs = = = = = = = = = = = 7.2 kHz 8.0 kHz 9.6 kHz 14.4 kHz 14.4 kHz 16.0 kHz 19.2 kHz 28.8 kHz 21.6 kHz 24.0 kHz 28.8 kHz 43.2 kHz FH = FH = FH = FH = FH = FH = FH = FH = FH = FH = FH = FH = 36 Hz 40 Hz 48 Hz 72 Hz 72 Hz 80 Hz 96 Hz 144 Hz 108 Hz 120 Hz 144 Hz 216 Hz The B regist er can be progr ammed for values gr eater than 20; however, since the low-p ass edge frequency FLP will then be more than the folding frequency Fs/2 aliasing can occur. When the B register is programmed for a valu e less t han 10, the ADC and the DAC conversions are not completed before the next frame-sync signal and the results are in error. The maximum sampling rate for the ADC channel is 43.2 kHz . The maximum rate for the DAC channel is 25 kHz . Note t hat th e MCLK of t he DSKpluS board is actually 10 MHz, so that the above numb ers are slig htly different . T he magnitude characterist ic of the band-pass anti-aliasing filter is shown below. ADC BAND-PASS RESPONSE 0 -1 0 \ T _ 2S-c ,, 's · l ktt.r: FCl. K . 144 kHz al ! ~ , " c ~ "" - 20 - 30 - 40 -so - 60 0 2 ~ f\ / 34 -Input F 567 -_ NOTE A : Ab50lute F,equency (1<Hl) • NonnaI<zed F'~ x " fCU( (l<Kz) Figure 5 -4 4 70 L ecture 2: Assembly Language Programming Introduction The application development system for the TMS320C54x chip consists of 1) a modular board the DSPKPlus (DSP Starter's Kit Plus) 2) an assembler (DSPKPLASM.EXE) 3) an application loader (LOADAPP.EXE) 4) debugger program (DSKP lus Explorer) DSKplus Board The diagram of the DSKpius development board contains the analog interface circuit TLC320AC01 ('AC01), IEEE.1l49. 1 emulation port (XDS51O) , host port interface (HP I), CPU and peripherals. Figure 1-1 . DSKplus Board Diagram mu ~ spea k '" Slandard l IB'" mini-jacks ' or direct micropIlone and conneclion Soc:keled 'lZV 10 PAle lor HP' appIlcallcr4 o (Q] J - - -.....J3 l llCD 11111 11 i b=;--..LJ OUT 0 UlI Cl2 g:z ICD 1:300 + + 8 0 0 ICD R53 ! "'IDSP ! _0 Fl350 - o R3li o ;~;~ 0 (Q]1II 11 11111 111 11 11111 111 o .P1 0 0 000000000000 000000000000 000000000 00 o R54 BulIerwd .-tal port (BSP) and hoet port Herface (HPt) conlroI signals XOS5 10 enUator port (lEEEll49.1 standanl) DSP extema l dala bus 1 71 I· Figure 1- 2. DSKplus Memory Map Program Data OOOOh oo7Fh oo80h Reserved (OVLY =1) V ooaOh Interrupts Communications kernel 0100h OOOOh Memory-mapped registers ooSFh 0180h OO6Oh SCratch-pad RAM On-chip DARAM 10K words (OVLY =1) Program RAM oo7Fh OOSOh 0800h SSP RAM block or program RAM Kimel bUff~r 10 words , i~ l000h looAh l800h On-<:hip DARAM (10K words) 27FFh 2800h HPI RAM block or program RAM External \ 27FFh 2800h Program RAM 27FFh o Reserved memory EFFFh FOOOh Reserved on-chip ROM External F7FFh FSOOh Reserved ROM (bootIoader) FF7Fh FF BOh FFFFh Reserved ROM interrupts FFFF 72 Common Object File Format (COFF) T he assembler and linker create object files that can be executed by a TMS320C54x device. The format is called Common Ob ject File Format (COFF) . Sections COFF object files contain three default sections: 1) .text section, which usually contains executable code 2) .data section, which usually contains initialized data 3) .bss section , which usually reserves space for uninitialized variables. Source Statement Format TMS320C54x assembly language source programs can obtain up to 200 characters per line. Program Source Statement Syntax A source stateme nt can contain four ordered fields. T he general syntax is as follows: Mnemonic synt ax (such as .data): [label] [:] mnemonic [operand list] [; comment] Algebraic syntax (such as B = B + 4123h): [label] [:] ins truction [; comment] Follow these guidelines: 1) All statements must begin with a label , a blank, an asterisk, or a semicolon. 2) Labels are optional; if used, t hey must begin in column 1. 3) One or more blanks must separate each field. 4) Comments are optional. Label Field Labels are optional. It must begin in column 1. A label can contain upto 32 alphanumeric characters (A-Z , a-z, 0-9, _ and $), and can be followed by a colon (:). If you don't use a label, t he first character position must contain a blank, a semicolon (;), or an asterisk (*) . Mnemonic Field The mnemonic field follows the label field. It can contain: 1) Machine-instruction mnemonic (such as ABS, MP Y, 8TH ) 2) Assembler directive (such as .data, .list, .set ) 3) Macro directive (such as .macro, .var, .merit ) 4) Macro call Operand Field The operand field is a list of operands that follow the mnemonic field. Operand Prefixes for Instructions # prefix - the operand is an immediate value. Example: Label: ADD # 123, B @ prefix - the ope rand is direct-memory addressed. Example: Label: @AR2 += # 10. * prefix - the operand is an indirect address. Example: Label: LD *AR4 , A; 3 73 Inst ructi on Field Th e instruction field is a combination of mnemonic and operand fi elds. Comment Field A comment can begin in any column. If it begins in column 1, it can st art with a semicolon (;) or asterisk (*). Comments th at begin anywhere else begin with a semicolon. Constants The assembler support s t he following const ants: 1) Binar y Integer. Ex ample : O1 B 2) Octal Integer. Exam ple: 010, 10Q 3) Decimal Integer. Example: - 32768 4) Hexadecim al Int eger. Example: 78h, OFH, O F xF 5) Floating-Point Number. Exa mple: -3.14e - 3 6) Assembly-T ime Constant. Example: AIDer! .set ARI 7) Character. Example: 'a' 8) Character St ring. Example: "sample program" Expressions Three main factors influence the order of expression evaluation: 1) Parentheses: Expressions in parentheses are always evaluated first: 8/{4/2) = 4 2) Precedence Groups: The assembler uses the precedence of the C language: 8+ 4/ 2=10 3) Left- to-Right Evaluation: T he expressions are evaluated as in the C language: 8/4 *2= 4 Expression Operators 1) Unary: plus (+), min us (-), l's complement C) . 2) Arithmetic: add (+), subtract (-), multiply (*), divide (/), modulo (%) "3) Shift left «, Shift right » 4) Relational: «), (», «=), (>=), (==), (!=) 5) Bitwise: AND (&), OR (-), Exclusive OR C) Invoking the Assembler To invoke the assembler enter the following: dskplasm500 [input file [object file [listing file]]][-options] 1) dskplasm500 is the command that invokes the assembler 2) input file names the assembly language source file. 3) object file names the object file that the assembler creates. 4) listing file names the optional listing file that the assembler can create. 5) options identifies the assembler options that you want to use. Some example options are: -c makes case insignificant in the assembly language -i specifies a directory where t he assembler can find files -I produces a listing file -m uses a macro libra ry 4 74 Mnemonic Inst ruction Set Here follow some of the most common inst ructions. 1) Load and Store Inst ructions: LD = Load accumulator with shift MVDD = Move data from data memory to dat a memory POP D = Pop top of stack to da ta memory PO RTR = Read data from port PORTW = Write d at a to port PSHD = P ush data memory value onto stack READA = Read program memory addressed by accumulator A SACCD = Store accumulator conditionally ST = Store T register STH = Store accumulator high into memory STL = Store accumulator low into memory WRITA = Write data memory addressed by accumulator A 2) Arit h meti c Instruct ions: ABS = Absolute value of accumulator ADD = Add to accumulator CMPS = Compare select maximum and st ore DADD = Double precision add MAC = Mult iply/accumulate without rounding MACA = Multiply by accumulator A and accumulat e MACR = Multiply/accumulate with rounding MAS = Multiply and subtract MASR = Multiply and subtract wit h rounding MAX = Accumulator maximum MIN = Accumulator minmum MPY = Multiply NORM = Normalization RND = Round accumulator SAT = Sat urate accumulator SQUR = Square SUB = Subtract from accumulator LDll 3) Parallel Instructions: MAC = Multiply accumulate with parallel load ST II ADD = Store accumulator and parallel add ST II LD = Store accumulator with parallel load ST II MAC = Store accumulator add parallel multiply/ accumulate 4) Logical Instructions: AND = AND with accumulator CMP L = Com plement accumulator OR = OR wit h accumulator 5 75 ROL = Ro ta te accumula tor left ROR = Ro tate accumula tor right XOR = Exclusive-OR with accumulator 5) Bit Manipulation Instructions: BIT = Test bit BITT = Test bit specified by T register 6) Application -Specific Funct ions ABDST = Absolute distance EXP = Accumulato r exponent FIRS = Symmetrical finite impulse response filter LMS = Leas t mean square inst ruct ion POLY = Polynomial evaluation SQDST = Squ are distance 7) Loop Inst ructions RPT = Repeat next instruction RPTB(D] = Block repeat 8) Program Control Instructions = Branch unconditionally BANZ(D] = Branch on auxiliary register not zero CALA(D] = Call subroutine at location specified by accumulator CC (D] = Call conditionally with optional delay IDLE = Idle until interrupt INTR = Software interupt NOP = No operation RC[D] = Return conditionally with optional delay RESET = Software reset B(D] 1) Assembler Directives that define sections ·bss = reserve space for variables in .bss section .dat a = begin assembling source code into the .data section .sect = defines a named section .setsect = initialize the section 's absolute address ·text = begin assembling into the .text section, which usually contains executable code ·usect = reserve space for variables in an uninitialized named section 2) Assembler Directives that initialize constants ·bes = reserves bits in the current section ·byte = place one or more bytes int o consecutive words of the current sectio n .field = place multiple-bit fields within a single word of memory .fl oat = place one or more floating point represent ations into the cu rr ent section .int = place one or more values into consecutive 16-bit fields in t he current section .long = place one or more 32-bit values into consecutive words in the current section .space = reserve a number of bits in the current section 6 76 .st ring = place 8-bit characters from a string into th e curr en t section .word = place 16-bit integers into th e currr ent secti on 3) Assembler Directives that format output listing .lengt h = set page length .list = restart source listing .nolist = stop source listing .opti on = opt ions for assembler output listing ·page = eject a page in source listing ·t it le = print a ti tle in the listing page heading ·wid th = set page widt h of source listing 4) Assembler Directives that reference other files .copy = read source stat ement from a different file .include = read source statement from a diffe rent file 5) Assembler Directives that control conditionally .end = terminat es assembly (optional statement) .if, .elseif, .else, .endif = conditional assemble a block of cod e .loop, .break, .endloop = repeatedly assemble a block of code 6) Assembler Direct ives th at define symbols .algebraic = tell the assembler that this file cont ains algebraic assembly source code .asg = assign character strings to substitution symbols .eval = perform arithmet ic on numeric substitution symbols .label = define a special symbol .set , .equ = equate a cons tant value to a symbol 7) Assembler Directives for macros . . macro, .endm = macro definition .mlib = provide the assembler with the name of a macro library Macros Usin g a macro is a three-step process: 1) Define th e macro. 2) Call the macro. 3) Expand the macro. A macro definition is a series of source statements in the following format: macro-name .macro [parameters] mod el statements or macro directives .endm 1) macro-name names the macro. 2) .macro identifies the source statement as the first line of a macro 3) parameters are opt ional substitution symbols t hat appear as operands 4) model statements are instructions or assembler directives that are executed each time th e macro is called 5) .endm terminates the macro definition 7 77 ;Experiment A: D ons t r at i on Program for sorting a l i st of numbers . em .sets ect " . text ", Ox500,0 ;Execut i bl e code in " . t ext " ;sectio n wil l beg in at Ox500 ; i n pro gram me mory um . s et s ect ". da ta " , Ox800,1 ; N ber s to be so r te d wi ll ;be gin at Ox8 00 in data memory .data .word . word .text .set 7 A RO ;Data section begins 4 ,5,1, 2 , 7 ,3,6,9 0 ,0,0,0 ,0,0,0 ,0 ;Execut i bl e code sec t io n begins ;Eight data point s so seven plus one for a ;total of ei ght execut ion steps per loop. ;Registers ARO and ARl are being used as ;two counters for the two neste d loops ;us ed in the sort. ;AR2 point s to the input data lo cat ion ;AR1 is r es et at the beginning of t he outer ;loop. ;AR3 points to the output data location ;A ccumulator A loads first dat a point ;which is shifted in the 31-16 (MSB) bit ; location ;Bits 0-15 (LSB) of accumulator A is loaded ;with value f r om output li st to compare / ;and sort . ;Main compare, select and store max command ;Data pointer is automatically incremented ;to span entire data r ange ;1f LSB > MSB the n keep MS B, sh i f t it into ;LSB, store it in AR4, and sh i f t it back ;else discard MSB by shifting LSB to MSB ;shift MSB to LSB and discard previous LSB ;A is temporary register during shifting R4 ;of accumulator A contents ar ray output count = #c ount = #array = #count l oop1 AR2 A Rl AR3 = #output R2+ « 16 A = *A A = A + *AR3 loop2 cmps(A, *AR3+) if (TC) goto low goto noshift A = A » 16 • low noshift AR4 = A A = GAR4 « 16 ; l oad next val ue of outp ut ar r ay in LSB = A + * AR3 ; check to se e if lo ops if (*A R1- ! = 0) got o l oop2 ;are complet ed and th en halt . if (*A - ! = 0) goto loopl RO nop ; i nf i ni te l oop got o st op . end A st op 8 78 __ " " ,_ ~ .... _ • • " . _ •_ _ , .• _ ,J,. _ _ . _ .. ... ~ _ _ . .... __ ... . . - . - .... ..... _ _ ~ .~~ c r· ... -• ... _: ~ 2.19.2.2 08 13 (RfW Bit) Reset and power-up procedu res set this bit to a 0, placing the device in the write mode. When this bit is set to 1, howev er, the previous data content of the register being addres sed is read out to the host from OOUT as the least significant 8 bits of the 16-bit secondary word. The first 8 bits remain set to O. Reading the data out is nondestructive, and the contents of the register remain unchanged . A. Write Mode (OS13 = 0) Data In. The data word to DIN has the following general form at in the write mode . 0815 1081 4 0 8 13 081 21 08 1110810 1080910808 0807 108061 08051 08041 08031 0 80 2 1 0801 10800 Cont rol Bits 0 Register Address Register Oata Data Oul. The shift clock shifts out all Osas the pattern to the host from DOUT. 0815 0814 0 8 13 08 12 0811 081 0 0809 0 8 08 0 8 07 0806 0 805 08 04 0 8 03 0802 080 1 0800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B. Read Mode (DS 13 = 1) Data In. The dat a word to DIN has the following form at to allow a register read. Phase shifts can also be done in the read mode. 08 15 10 8 14 08 13 081210 8 11 10810 08091 0 8 08 0807 10806 108051 08041 0803 1 08021 08011 0800 Control Bits I 1 Register Address Ignored Data Out. The sh ift clock clocks out the data of the register addressed from DOUT in the read mode in the 8 LSBs . 08 15 0 8 14 0813 081 2 0811 0810 0809 0808 0 80710806108051080410803108021080110800 0 0 0 0 0 0 0 0 Register Oata 2.20 Internal Register Format 2.20.1 Pseudo-Register 0 (No-Op Address) This address represents a no-operation command . No register 1/0 operation takes place, so the device can receive secondary commands for phase adjustment without reprogramming any register. A read of the no-op is O. The format of the command word is as follows: 081510814 0 8 13 0812 0811 0810 0809 0808 0807 0806 0805 0804 0803 0802 0801 0800 Control Bits X 0 0 0 0 0 X X X X X X X X 2.20.2 Register 1 (A Register) The following command loads DS07 (MSB) - OSOO into the A register. 0 8 15 10 8 14 0813 0812 0811 0810 0809 0808 0 8 07 10 8 06 10 805 10 8 0410 803 10 8 021 080 1 10 800 Control Bits R/W 0 0 0 0 1 Register Data The data in 0807 - DSOO determines the division of the master cloc k to produce the internal FCLK. FCLK frequency = MCLK/(A register contents x 2) 2-20 79 The default value of the A-register data is decimal 18 as shown below. 08 07 080 6 0805 0 804 0 803 0 802 0801 0800 0 0 0 1 0 0 1 0 2.20.3 Register 2 (8 Register) The following command loads 0807 (M8 B) - 0800 into the B register. 0 81 5 10 814 081 3 08 12 08 11 0810 0809 08 08 080 7 1080 61 080 5 \ 0 804 108 03 108 02 10 8 01 10800 1 0 Control Bits RfW 0 0 0 Register Oata The data in 0807 - 0 800 controls the division of FCLK to generate the conversi on clock as given in equation 20: Conversion frequency = FCLK/ (B register contents) MCLK 2 x A register contents x B register contents The default value of the B-register data is decimal 18 as shown below. 0807 08 06 080 5 0 8 04 0 803 0802 0 8 01 0800 0 0 0 1 0 0 1 0 (20) 2.20.4 Register 3 (A' Register) The followi ng command contains the A'-register address and loads D80 7(M8 B) - D800 into the A' registe r. 08 15 10 8 14 0813 08 12 081 1 0810 0809 0808 08 07 108 061 080 51 0 8 041 08 031 0802 1080 1 1080 0 Control Bits RtW 0 0 0 1 1 Register Data The data in 0807 - 0 800 is in 2s-complement format and controls the number of master-clock periods that the samplin g time is shifted. The default value of the A'-register data is 0 as shown below. 0 8 07 0 0506 0805 0804 08 03 0 802 0 8 01 0800 0 0 0 0 0 0 0 2-2 1 80 ·. ~ , . __ _ -' "",--. _ ~ . _,--- , -~ ' -~ ". 2.20.5 Register 4 (Ampl ifier Gain-Select Register) Th e following command contains the amplifier gain-select register addre ss with selection code for the monit or output (OS05- 0 S04), analog input (OS03- 0 S02), and analog output (OS01 -0S00) programmable gains. OS151 0 S14 OS13 OS12 OS11 OS10 Co ntrol Bits OS09 OS08 OS07 OS06 OS05 OS04 OS0 3 OS02 OS01 OSO O 0 0 X X ~ ~ ~ ~ R m 0 0 1 * 0 0 1 1 * 0 1 0 1 ~ ,;. * * * Monitor output gain =squelch Moni tor output gain =0 dB Monitor output gain =-8 dB Monitor output gain =- 18 dB Analog input gain =squelch Analog input gain =0 dB Anal og input gain =6 dB Analog input gain 12 dB Analog output gain =squelch Analog output gain =0 dB Analog output gain =- 6 dB Analog output gain 12dB ~ ~ ~ ::' r--- 0 0 1 0'\ 1 ~ ~ ~ ~ 0 1 0 0 1 1 0 1 0 1 The default value of the monitor output gain is squelch, which corresponds to data bits DS05 and 0804 equal to 00 (binary). The default value of the analog input gain is 0 dB, which corresponds to data bits DS03 and OS02 equal to 01 (binary). The default value of the analog output gain is 0 dB, which corresponds to data bits DS01 and OSOO equal to 01 (binary). The default data value is shown below. 0807 0806 0805 0 804 0803 0802 OSOl OSOO :.~ 0 0 0 0 0 1 0 1 2.20.6 Register 5 (Analog Configuration Register) The follow ing command loads the analog configuration register with the individual bit functions described beiow. 0815108 14 D813 OS12 Control Bits osn 0 OSlO OS09 OS08 OS07 OS06 0805 0804 0803 0802 080 1 D800 0 RiW 0 1 1 X X X X ~ * 0 ~ ~ * * * Must be set to 0 High-pass filter disabled High-pass filter enabled Analog loopback enabled Enables IN + and IN - (disables AUXIN + and AUXIN -) Enables AUXIN + and AUXIN- (disables IN + and IN - ) Enabl e analog input summing 1 0 ~ ~ ~ 0 0 0 1 0 1 1 • 1 The default value of the high-pass-filter enable bit is 0, which places the high-pass filter in the signal path. The default values of 0 801 and DSO are 0 and 1 which enables IN + and IN-. O 2- 22 81 The power-up and reset conditions are as shown below. DS03 0 DS02 DS01 DSO O 0 0 1 In the read mode, eight bits are read but the 4 LSBs are repeated as the 4 MSBs . 2.20.7 Register 6 (Digital Configuration Register) The following command loads the digital configurat ion register with the individual bit functions described below. DS 1S1 DS14 DS13 DS 12 DS 11 DS 10 Control Bits DS09 DS08 1 0 DS07 DS06 DSOS DS04 DS03 DS02 DS01 DSOO RJW 0 0 1 X X ADC and DAC conversio n free run Inactive FSD output disable Enable 16-Bit mode , ignore primary LSBs Normal ope ration Force secondary communications Normal opera tion Software reset (upon reset , this bit is automatically reset to 0) Inactive reset Softwa re power-down active (automatically reset to 0 after PWR DWN is cycled high to low and back to high) Power-down function external (uses PWR DWN) • • * 1 0 * * * * * • • 1 0 • • 1 0 • • 1 0 • • 1 0 • • 1 0 The default value of OS07- OSOO is 0 as shown below. DS07 0 DS06 DSOS DS04 DS03 DS02 DS01 DSOO 0 0 0 0 0 0 0 2.20.8 Register 7 (Frame-Sync Delay Register) The following command contains the frame-sync delay (FSO) register address and loads DS07 (MSB)-OSOO into the FSO register. The data byte (OS01- DSO ) determines the number of SCLKs O between FS and the delayed frame-sync signal, FSO. The minimum data value for this register is decimal 18. DS 1SIDS1 4 OS13 DS12 Control Bits Rm 0 OS11 OS10 0 1 OS09 OS08 1 1 DS071 OS06 1 osos]OS041 DS031 OS021 DS011 OSOO Register Data The default value of OS07 - OSOO is 0 as shown below. OS07 OS06 DSOS OS04 OS03 OS02 OSOl OSOO 0 0 0 0 0 0 0 0 When using a slave device, register 7 must be the last register programmed. 2-23 82 2.20.9 Register 8 (Frame-Sync Numbe r Register) The following command cont ains the frame-sync number (F8 N) register address and loads 0807 (M8 B)- 0800 into the F8N register. The data byte determines the number of frame-sync signals genera ted by the TLC320AC01. This number is equal to the number of slaves plus one. 051510514 0513 05 12 0 8 11 05 10 0 5 09 0508 0 5 07 10 5 06 10 8 05 10 5 04 10 5 03 10 502 10 5 0 1 10 8 00 Control Bits R!W 0 1 0 0 0 Register Data The default value of 0807 - 08 00 is 1 as shown below. 0807 0 8 06 0 8 05 0504 0 8 03 08 02 080 1 0500 0 0 0 0 0 0 0 1 2-2 4 83 84 ...
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