ECE 429 Lab Report

ECE 429 Lab Report - / /Stage 1 begins module dreg(qout, d,...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
//////////////////////////////////////////////////////////////////////// //Stage 1 begins module dreg ( qout , d , clk ); // I/O port declarations input d , clk ; output qout ; reg qout ;
Background image of page 2
@( posedge clk ) qout <= d ; endmodule module dreg4 ( qout , d , clk ); input [ 3 : 0 ] d ; input clk ; output [ 3 : 0 ] qout ; dreg d3 ( qout [3] , d [3] , clk ); dreg d2 ( qout [2] , d [2] , clk ); dreg d1 ( qout [1] , d [1] , clk ); dreg d0 ( qout [0] , d [0] , clk ); endmodule module xor4 ( xout , a , B ); input a ; input [ 3 : 0 ] B ; output [ 3 : 0 ] xout ; xor x3 ( xout [3] , a , B [3] ); xor x2 ( xout [2] , a , B [2] ); xor x1 ( xout [1] , a , B [1] ); xor x0 ( xout [0] , a , B [0] ); endmodule module level1 ( xoredA , xoredB , in , A , B , invertA , invertB , clk ); output [ 3 : 0 ] xoredA , xoredB ; output in ; input clk , invertA , invertB ; input [ 3 : 0 ] A ; input [ 3 : 0 ] B ; wire invAout , invBout ; wire [ 3 : 0 ] Aout ; wire [ 3 : 0 ] Bout ; wire in ; dreg inv_a_reg ( invAout , invertA , clk ); dreg
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 10

ECE 429 Lab Report - / /Stage 1 begins module dreg(qout, d,...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online