CS231_FA10_HW6_Solution

# CS231_FA10_HW6_Solution - CS231 Fall 2010 ...

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Unformatted text preview: CS231 Fall 2010  Homework 6 Solution  Due at 5:00pm, Wednesday, Oct. 27th, 2010  in CS231 HW boxes in Siebel Center’s basement    Introductory notes:  • Write your name, your netID, and "CS 231" clearly on the first page.  • You must follow the Formatting Guidelines listed on the assignments page  or your score will be penalized.  • There are a total of 5 questions in this homework worth a total of 100 points.   • You must work individually on homework.  You may discuss material with  other students, the TAs, and the Professor for the purpose of understanding,  but your work must be your own.  See the syllabus for our cheating policy.  • The general guideline for doing assignments is that you must convince us  that you know what you're doing. To receive credit, make sure your solutions  are neat and legible, and that you show enough work.  • Turn in the assignment in the HW boxes. The HW boxes are located in the  east end of the basement of Siebel Center (near the vending machines).  Please do not submit it anywhere else. You may turn in the assignment up to  24 hours after the due date i.e. by Thursday, Oct. 28th, at 5:00pm, but you  will receive a 20% late penalty. Homework will NOT be accepted after this  (as this is when we will post the solutions). See the syllabus for our late  policy.    • You are encouraged to use book problems for practice.  • Please staple all your pages together with a real, metal staple.  • Feel free to ask us questions at office hours or on the course newsgroup.                                        1. (12 pts) Flip‐Flop True or False.  Circle one.   (a) True / False   For a D flip‐flop, the next state is always set equal to the D  input when C receives a positive edge.  (b) True / False   For a T flip‐flop, when the present state Q=0 goes to the  next state Q=1, the required T input is T=0.  (c) True / False   A JK flip‐flop is presently in the SET state and must go to  the RESET state on the next clock pulse. J must be 1 and K must be X (don't care).  (d) True / False   JK flip‐flop is presently in the RESET state and must remain  RESET on the next clock pulse. Then J must be 0 and K must be X.    2. (24 pts) Any type of flip flop can be implemented using any other type of flip flop  and some additional gates:  a. (8 pts) Construct a T flip‐flop using a JK flip‐flop.  T  Q(t)  Q(t+1)  J  K  0  0  0  0  x  0  1  1  x  0  1  0  1  1  x  1  1  0  x  1  minimal SOP expressions: J = T    K = T     b. (8 pts) Construct a JK flip‐flop using a D flip‐flop and minimal combinational  logic.  J  K  Q(t)  Q(t+1)  D  0  0  0  0  0  0  0  1  1  1  0  1  0  0  0  0  1  1  0  0  1  0  0  1  1  1  0  1  1  1  1  1  0  1  1  1  1  1  0  0  minimal SOP expression: D = JQ' + K'Q      c. (8 pts) Construct a D flip‐flop using a JK flip‐flop and some combinational  logic.  D  Q(t)  Q(t+1)  J  K  0  0  0  0  x  0 1  0  x  1  1  0  1  1  x  1  1  1  x  0    minimal SOP expressions: J = D    K = D'   3. (20 pts) Analyze the following sequential circuit. CLK is the clock signal.       A.(8 pts) Fill in the state table:  Q  X  Y  0  0  0  0  1  1  1  1  0  0  1  1  0  0  1  1  0  1  0  1  0  1  0  1   0   0   0    1    0    0    0    1     Q+  0  0   0    0    1    1    1    1   S    B.(8 pts) From the state table, draw the state diagram.  Label your states with  the current values of Q (that is, 0 or 1).  The arrows between should be  labeled with input (xy) / output (s).        C.(4 pts) Starting in state Q = 0, which states are not reachable, if any?    Starting in state Q=0, all states are reachable. (Starting in state 1, all states are also reachable) 4. (20 pts): Sequential Circuit Analysis  Below is a diagram made of two JK flip‐flops. There are no inputs and the outputs  are just the flip‐flop states Q1 and Q0 themselves.      A (12 points). Fill in the rest of the state table below for this circuit.  Current State  Q0  0  0  1  1     B (8 points). Draw the state diagram for this circuit. Since there are no  inputs or outputs, you do not need to label your state transition arrows.     Q1  0  1  0  1  J0  1  1  0  0  Flip‐flop inputs  K0  1  1  0  0  J1  1  1  0  1  K1  0  1  0  0  Next State  Q0  1  1  1  1  Q1  1  0  0  1    5. (24 pts): Sequential Circuit Analysis II  Analyze  the  following  circuit  diagram  made  of  two  JK  flip‐flops  and  answer  the  questions that follow. There  is one input variable X and two state variables Q1 and  Q2 for FF1 and FF2 respectively.    (A). (18 points) Fill in the rest of the following table.   Present  Input  Next State  Q2  0  0  0  0  1  1  1  1  Q1  0  0  1  1  0  0  1  1  X  0  1  0  1  0  1  0  1  Q2  0  1  0  0  1  0  1  1  Q1  0  1  1  1  1  0  0  1  (B).  (6  points)  If  the  initial  state  is  11,  does  the  circuit  have  any  unused  state?  If  yes,  name  the  unused  state.  If  no,  justify  that  there  is  no  unused  state.   Yes, state 01 is unused as it is not reachable through any other state.  ...
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## This note was uploaded on 11/08/2010 for the course CS 231 taught by Professor - during the Spring '08 term at University of Illinois at Urbana–Champaign.

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