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ECE3140sp09_HW5_sol

ECE3140sp09_HW5_sol - ECE 3140/CS 3420 Spring 2009 Homework...

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ECE 3140 /CS 3420 Spring 2009 Homework 5 Solutions Problem 1. (10 points) Patterson & Hennessy Exercises 4.16.4 (part b only) sw \$0,0(\$1) WB sw \$0,4(\$1) MEM WB add \$2,\$2,\$4 EX MEM WB beq \$2,\$0,Loop ID EX MEM WB add \$1,\$2,\$3 IF ID EX MEM WB sw \$0,0(\$1) IF ID EX MEM sw \$0,4(\$1) IF ID EX add \$2,\$2,\$4 IF ID beq \$2,\$0,Loop IF Patterson & Hennessy Exercises 4.16.5 (part b only) In a particular clock cycle, a pipeline stage is not doing useful work if it is stalled or if the instruction going through that stage is not doing any useful work there. In the pipeline execution diagram from 4.16.4, a stage is stalled if its name is not shown for a particular cycles, and stages in which the particular instruction is not doing useful work are marked in red. Note that a BEQ instruction is doing useful work in the EX stage, because it is determining the correct value of the next instruction’s PC in that stage. We have: Cycles per loop iteration Cycles per loop iteration Cycles in which all stages do useful work % of cycles in which all stages do useful work 5 1 20% Problem 2. (x points) Patterson & Hennessy Exercises 4.17.5 (part a only) The time for the combined EX + MEM stage is max(90ps,130ps). The clock cycle time of the single-cycle datapath is the sum of logic latencies for the four stages (IF, ID, the combined EX + MEM stage, and WB) = 100ps + 120ps + 130ps + 60ps = 410ps.

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