# 2 - CSE140 Components and Design Techniques for Digital...

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1 CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing

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2 Review: Mux/Demux Example F(A,B,C) = Π M(0,2,4)
3 Hazards Glitch – unwanted pulse on the output Circuit with a potential for a glitch has a hazard Three types: – Static-0 : output should be 0 but has a 1 glitch – Static-1 : output should be 1 but has a 0 glitch – Dynamic: transition 0->1 or 1->0 with a glitch

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4 Eliminating Hazards Example F(A,B,C,D)= Σ m (1,3,5,7,8,9,12,13) Test two single bit input transitions: – 1100 -> 1101 – 1100 -> 0101 A C’ D Z D 0 0 1 1 1 1 1 1 A 1 1 0 0 0 0 0 0 B C
5 CSE140: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing

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6 Conversion to NAND/NOR gates Use De Morgan’s: – A’ + B’ = (A • B)’ – A’ • B’ = (A+B)’ Two-level NAND-NAND example:
7 Conversion between forms Example: map AND/OR network to NOR/NOR network Use De Morgan’s: – A’ + B’ = (A • B)’ – A’ • B’ = (A+B)’ A B C D Z

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8 Multiple-Output Circuits Many circuits have more than one output Can give each a separate circuit, or can share gates Ex: F = ab + c’, G = ab + bc Option 1: Separate circuits Option 2: Shared gates
A B C D E F G X Multi-level logic x = A D F + A E F + B D F + B E F + C D F + C E F + G – reduced sum-of-products form – already simplified – 6 x 3-input AND gates + 1 x 7-input OR gate (that may not even exist!) – 25 wires (19 literals plus 6 internal wires) x = (A + B + C) (D + E) F + G – factored form – not written as two-level S-o-P – 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate – 10 wires (7 literals plus 3 internal wires)

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10 Multiple-Output Example: BCD to 7-Segment Converter a = w’x’y’z’ + w’x’yz’ + w’x’yz + w’xy’z + w’xyz’ + w’xyz + wx’y’z’ + wx’y’z abcdefg = 1111110 0110000 1101101 a f b d g e c (b) (a) b = w’x’y’z’ + w’x’y’z + w’x’yz’ + w’x’yz + w’xy’z’ + w’xyz + wx’y’z’ + wx’y’z
11 CSE140: Components and Design Techniques for Digital Systems Regular logic implementation Tajana Simunic Rosing

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12 + 2x2 AOI gate symbol
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## This note was uploaded on 11/10/2010 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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2 - CSE140 Components and Design Techniques for Digital...

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