4 - CSE140: Components and Design Techniques for Digital...

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1 CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing
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2 Bit Storage Overview D flip-flop D latch master D latch servant DmQm Cm Ds D Clk Qs’ Cs Qs Q’ Q S R D Q C D latch Feature: Only loads D value present at rising clock edge, so values can’t propagate to other flip-flops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR – but gate count is less of an issue today. Feature: SR can’t be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store. S1 R1 S Q C R Level-sensitive SR latch Feature: S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden. R (reset) S (set) Q SR latch Feature: S=1 sets Q to 1, R=1 resets Q to 0. Problem: SR=11 yield undefined Q.
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3 Flip-Flop Set, Reset and Active Hi/Low Inputs – Synchronous reset: clears Q to 0 on next clock edge – Synchronous set: sets Q to 1 on next clock edge – Asynchronous reset: clear Q to 0 immediately - see diagram – Asynchronous set: set Q to 1 immediately D Q’ Q R Q’ AR D Q Q’ AS AR D Q cycle 1 cycle 2 cycle 3 cycle 4 clk D AR Q D Q’ Q R
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4 Flip-Flop Types SR flip-flop: like SR latch, but edge triggered JK flip-flop: like SR (S J, R K) – But when JK=11, toggles – 1 0, 0 1 T flip-flop: JK with inputs tied together – Toggles on every rising clock edge Previously utilized to minimize logic outside flip-flop – Today, minimizing logic to such extent is not as important – D flip-flops are thus by far the most common 3.5
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5 FF Types
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6 Non-Ideal Flip-Flop Behavior Can’t change flip-flop input too close to clock edge – Setup time: time that D must be stable before edge Else, stable value not present at internal latch – Hold time: time that D must be held stable after edge Else, new value doesn’t have time to loop around and stabilize in internal latch clk D clk D setup time hold time R S D C u D latch Q Q’ 1 2 3 4 5 6 7 C D S u R Q’ Q
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This note was uploaded on 11/10/2010 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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4 - CSE140: Components and Design Techniques for Digital...

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