5 - CSE140: Components and Design Techniques for Digital...

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Sources: TSR, Katz, Boriello, Vahid, Perkowski 1 CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 2 Overview Where we’ve been Finite State Machine definition Mealy vs. Moore FSM Design procedure for FSMs 1. Capture FSM 2. Select architecture 3. Encode the states 4. Create state table 5. Implement combinational logic What is next Examples of FSM design and analysis FSM optimization State assignment and partitioning
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Sources: TSR, Katz, Boriello, Vahid, Perkowski FSM design example T = 0 if Q=Q+ T = 1 else D = 0 if Q+=0 D = 1 if Q+=1
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 4 CSE140: Components and Design Techniques for Digital Systems FSM Optimization Tajana Simunic Rosing
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Sources: TSR, Katz, Boriello, Vahid, Perkowski State tables State minimization State assignment Combinational logic optimization netlist identify and remove equivalent states assign unique binary code to each state use unassigned state-codes as don’t care Goal : remove redundant states which can not be observed from the FSM I/O behavior Why : 1. Reduce number of FFs 2. Increase # unassigned state codes FSM Optimization Flow Chart
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 6 Successive partitioning algorithm for state minimization Goal identify and combine states that have equivalent behavior Algorithm sketch 1. place all states in one set 2. initially partition set based on the output behavior 3. successively partition the resulting subsets based on next state transitions 4. repeat (3) until no further partitioning is possible states left in the same set are equivalent Polynomial time procedure
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 7 ( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 ) ( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 ) Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1 S2 0 0 0 S1 S3 S4 0 0 1 S2 S5 S6 0 0 00 S3 S0 S0 0 0 01 S4 S0 S0 1 0 10 S5 S0 S0 0 0 11 S6 S0 S0 1 0 Method of successive partitions
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 8 Input Present Next State Output Sequence State X=0 X=1 X=0 X=1 Reset S0 S1' S1' 0 0 0 + 1 S1' S3' S4' 0 0 00+10 S3' S0 S0 0 0 01+11 S4' S0 S0 1 0 Minimized FSM S0 S1’ S3’ S4’ X/0 1/0 1/0 0/1 0/0 X/0 Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1 S2 0 0 0 S1 S3 S4 0 0 1 S2 S5 S6 0 0 00 S3 S0 S0 0 0 01 S4 S0 S0 1 0 10 S5 S0 S0 0 0 11 S6 S0 S0 1 0 ( S0 ) ( S1 S2 ) ( S3 S5 ) ( S4 S6 )
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 9 Basic Concepts x S a b c d a b c d 1 3 4 2 1 1 1 2 4 0 3 6 6 0 1 4 6 1 5 0 0 1 5 2 1 6 3 2 3 0 0 1 Compatiblity: Si, Sj are compatible if for each input they have consistent outputs, and their successors are the same or compatible. Conditionally compatible
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5 - CSE140: Components and Design Techniques for Digital...

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