7 - CSE140: Components and Design Techniques for Digital...

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Sources: TSR, Katz, Boriello, Vahid 1 CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing
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Sources: TSR, Katz, Boriello, Vahid 2 Outline Today: Memory ROM RAM FIFO Queue Next: Register Transfer Level Design
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Sources: TSR, Katz, Boriello, Vahid 3 CSE140: Components and Design Techniques for Digital Systems Memory Tajana Simunic Rosing
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Sources: TSR, Katz, Boriello, Vahid 4 Memory: basic concepts Stores large number of bits m x n : m words of n bits each – k = Log 2 ( m ) address input signals – or m = 2^k words – e.g., 4,096 x 8 memory: 32,768 bits 12 address input signals 8 input/output data signals Memory access – r/w: selects read or write – enable: read or write only when asserted – multiport: multiple accesses to different locations simultaneously m × n memory n bits per word m words enable 2 k × n read and write memory A 0 r/w Q 0 Q n-1 A k-1 memory external view
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Sources: TSR, Katz, Boriello, Vahid 5 Write ability/ storage permanence Traditional ROM/RAM – ROM read only, bits stored without power – RAM read and write, lose stored bits without power Distinctions blurred – Advanced ROMs can be written to e.g., EEPROM – Advanced RAMs can hold bits without power e.g., NVRAM Write ability and storage permanence of memories, showing relative degrees along each axis (not to scale). External programmer OR in-system, block-oriented writes, 1,000s of cycles Battery life (10 years) Write ability EPROM Mask-programmed ROM EEPROM FLASH NVRAM SRAM/DRAM Storage permanence Nonvolatile In-system programmable Ideal memory OTP ROM During fabrication only External programmer, 1,000s of cycles External programmer, one time only External programmer OR in-system, 1,000s of cycles In-system, fast writes, unlimited cycles Near zero Tens of years Life of product
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Sources: TSR, Katz, Boriello, Vahid 6 Random Access Memory (RAM) RAM – Readable and writable memory – Logically the same as register file • RAM just one port; register file two or more – RAM vs. register file • RAM is larger • RAM stores bits using a bit storage vs. FFs • RAM implemented on a chip in a square – keeps longest wires (hence delay) short 32 10 data addr rw en 1024 × 32 RAM 32 4 32 4 W_data W_addr W_en R_data R_addr R_en 16 × 32 register file Register file RAM block symbol
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Sources: TSR, Katz, Boriello, Vahid 7 RAM Internal Structure Similar internal structure as register file – Decoder enables appropriate word based on address inputs – rw controls whether cell is written or read – Let’s see what’s inside each RAM cell 32 10 data addr rw en 1024x32 RAM addr0 addr1 addr(A-1) clk en rw Let A = log 2 M to all cells wdata(N-1) rdata(N-1) wdata(N-2) rdata(N-2) wdata0 rdata0 bit storage block (aka “cell”) word word RAM cell word enable word enable rw data cell data a0 a1 d0 d1 d(M-1) a(A-1) e AxM decoder enable
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Sources: TSR, Katz, Boriello, Vahid 8 Static RAM (SRAM) - writing “Static” RAM cell – 6 transistors (recall inverter is 2 transistors)
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This note was uploaded on 11/10/2010 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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7 - CSE140: Components and Design Techniques for Digital...

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