8 - CSE140 Components and Design Techniques for Digital...

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Sources: TSR, Katz, Boriello, Vahid, Perkowski 1 CSE140: Components and Design Techniques for Digital Systems RTL Design Process Tajana Simunic Rosing
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 2 Announcements and Outline CAPE season opens Monday, 5/24!!!! – Please go to http://www.cape.ucsd.edu/ and fill out your evaluation Pick up graded homework at my assistant’s office – Check webct grades; make sure everything is correct – Graded/regraded exams are in my office Next exam on 6/3, class time – Everything covered in lectures, whole book & all handouts – Format: • Problems similar to HW and previous exams • May have multiple choice and/or T/F questions on the assigned reading – Tuesday, 6/1 lecture will go over the previous year’s final and additional examples Discussion session this week will go over RTL problems Next: More RTL examples, CPU design
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 3 RTL Design Method 5.2
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 4 RTL for Datapath & Control
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 5 RTL Design example: Laser-Based Distance Measurer Laser-based distance measurement – pulse laser, measure time T to sense reflection – Laser light travels at speed of light, 3*10 8 m/sec – Distance is thus D = T sec * 3*10 8 m/sec / 2 Object of interest D 2D = T sec * 3*10 8 m/sec sensor laser T (in seconds)
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 6 Step 4: Deriving the Controller’s FSM FSM has same structure as high- level state machine – Inputs/outputs all bits now – Replace data operations by bit operations using datapath 300 M Hz Clock D B L S 16 to displ ay from but ton Controller to laser from sensor Datapath Dreg_clr Dreg_ld Dctr_clr Dctr_cnt Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt S0 S1 S2 S3 L = 0 L = 1 B’ S’ B S S4 Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits) Local Registers: Dctr (16 bits) S0 S1 S2 S3 D = 0 L=0 Dctr = Dctr + 1 Dctr = 0 B’ S’ B S D = Dctr / 2 (calculate D) S4 Dreg_clr = 1 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser off) (clear D reg) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 1 Dctr_cnt = 0 (clear count) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser on) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 1 (laser off) (count up) Dreg_clr = 0 Dreg_ld = 1 Dctr_clr = 0 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting)
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 7 RTL Design Method Example Soda dispenser c : bit input, 1 when coin deposited a : 8-bit input having value of deposited coin s : 8-bit input having cost of a soda d : bit output, processor sets to 1 when total value of deposited coins equals or exceeds cost of a soda a s c d Soda dispenser processor 25 1 0 25 1 1 50 0 0 0 0 tot: tot: 50
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Sources: TSR, Katz, Boriello, Vahid, Perkowski 8 Step 1: Capture High-Level State Machine Declare local register tot Init state: Set d=0, tot=0 Wait state: wait for coin If see coin, go to Add state Add state: Update total value: tot = tot + a Remember, a is present coin’s value Go back to Wait state In Wait state, if tot >= s, go to Disp
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8 - CSE140 Components and Design Techniques for Digital...

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