hw5 - of 20 ns, a propagation delay of 15ns, and a hold...

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CSE140 Spring 2010, Homework #5 CSE140 Homework #5 Due date: 05/04/2010 You must SHOW ALL STEPS for obtaining the solution. Reporting the correct answer, without showing the work performed at each step will result in getting 0 points for that problem. 1. Determine the maximum frequency of the clock for the given details: T setup = 2ns T pd = 2ns T hold = 1.5ns T AND/OR = 1ns (AND/OR gates delay) Clk Clk Clk
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2. Given the following circuit, where the D-FF have a worst-case set up time
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Unformatted text preview: of 20 ns, a propagation delay of 15ns, and a hold time of 5ns, and the delay in the XOR/XNOR gates is 10ns. Find the maximum allowable frequency of this circuit. 3. 4. The FSM is defined by the following state transition table: PRESENT STATE Q1 Q0 NEXT STATE W = 0 W = 1 Q1 + Q0 + Q1 + Q0 + OUTPUT 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 Derive the next state and output equations. TEXTBOOK PROBLEMS: 5. 6.18 6. 6.23 7. 7.1 8. 7.4...
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This note was uploaded on 11/10/2010 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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hw5 - of 20 ns, a propagation delay of 15ns, and a hold...

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