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hw5sol

# hw5sol - p T delay and T su in the this inequality we get T...

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SOLUTIONS HW5: 1. Critical path: OR -> AND -> D-FF: T period > T pd + T OR + T AND + T setup = 2+1+1+2=6ns Frequency < 1/6ns 2. In order to determine the clock frequency we need to find the lower bound for T period . The inequality for T period is (page 325, text book): T period > T p + T delay + T su where T delay is the delay of the combinational circuit part. In our case it is the delay of both XOR and the XNOR, (10ns + 10ns =20ns). By plug in the values of T

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Unformatted text preview: p , T delay and T su , in the this inequality, we get T period > 15ns + 20ns + 20 ns T period > 55ns The maximum allowable frequency is 1/55ns = 18.1MHz 3. 4. K-Map for Q1 + Q1 + = Q0’Q1’ + Q1W’ K-Map for Q0 + Q0 + = Q0’Q1’W Since the given FSM is a Moore machine, the output depends only on its current state. Z = Q0Q1 5. 6. 7. 8....
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