sample_midterm_2_sol

# sample_midterm_2_sol - First Name Last Name PID CSE 140...

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F i r s t N a m e : L a s t N a m e : P I D : CSE 140 Midterm 2 Solution Tajana Simunic Rosing Winter 2009 z Do not start the exam until you are told to. z Turn off any cell phones or pagers. z Write your name and PID at the top of every page. Do not separate the pages. z This is a closed-book, closed-notes, no-calculator exam. You many only refer to one page of your own notes. z Do not look at anyone else’s exam. Do not talk to anyone but an exam proctor during the exam. z If you have a question, raise your hand and an exam proctor will come to you. z You have 80 minutes to finish the exam. When the time is finished, you must stop writing. z Write your answers in the space provided. z To get the most partial credit, clearly and neatly show all steps of your work. 1. 15 points 2. 15 points 3. 15 points 4. 15 points 5. 20 points 6. 20 points 7. 10 points Total (100 points) (+10 bonus)

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F i r s t N a m e : L a s t N a m e : P I D : Problem 1 (15 points) A sequential circuit is shown in the figure below, within which Logic* represents a small piece of combinational logic. The timing characteristics of the gates and flip-flops are specified as follows. a) If the clock cycle time is 8ns, what range should the Logic* delay fall into in order to guarantee the correct timing of the circuit? Solution: the critical path is FF1 inverter OR gate Logic* AND gate FF3 For correct timing, the following condition must be satisfied: D FF1 + D inverter + D or + D logic* + D and + T setup < T cycle T setup < T cycle – (D FF1 + D inverter + D or + D and + T setup ) T setup < 8 – (2 + 0.5 + 1 + 1 + 1.5) = 2 b) Due to some design error in the clock generator, the CLK signal of
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sample_midterm_2_sol - First Name Last Name PID CSE 140...

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