exam_final_08

exam_final_08 - Department of Electrical and Computer...

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Department of Electrical and Computer Engineering UNIVERSITY OF BRITISH COLUMBIA EECE 480 MICROELECTRONIC DEVICES FINAL EXAM, December 5, 2008 Time: 3 hours ALL QUESTIONS MAY BE ATTEMPTED. A mark of greater than 50/50 is possible. Notes and non-programmable calculators are allowed. Programmable calculators, telecommunications devices and computers are NOT allowed. This exam consists of 3 pages. Information on CMOS90 technology: V DD =1 . 0V; L =90nm; t ox =2 . 3nm; ± ox =3 . 9 ± 0 ; N A =8 . 3 × 10 17 cm - 3 ; µ ef = 230 cm 2 (Vs) - 1 ; v sat =7 × 10 6 cm/s. Information on CMOS65 technology: V DD =1 . 0V; L =65nm; t ox =1 . 7nm; ± ox =3 . 9 ± 0 ; N A =2 . 6 × 10 18 cm - 3 ; µ ef = 600 cm 2 (Vs) - 1 ; v sat =9 × 10 6 cm/s. Other information: χ =4 . 1eV for Si; ± r =11 . 9forS i ; χ =4 . 07 eV for GaAs. h =6 . 63 × 10 - 34 Js; k B T =0 . 0259 eV; q =1 . 6 × 10 - 19 C; ± 0 =8 . 85 × 10 - 12 F/m; m 0 =9 . 11 × 10 - 31 kg. 1. [12 marks] (a) Over the last few decades, the trend in Si MOSFETs has been to reduce the gate length, the oxide thickness, and the source/drain-junction depth, and to increase the body doping density. Explain why each of these four parameters has been systematically changed. (b) In recent years, the trend has been for the ‘long-channel threshold voltage’ to increase, e.g. ,fo r CMOS90 N-FETs V T 0 is about 0.25 V, whereas it is about 0.4 V for CMOS65 N-FETs. Why (not how) is V T 0 being deliberately designed to be higher as CMOS technology evolves in the modern era? (c) The parameters for CMOS45 are not yet well known, but one might expect a thicker high-k dielectric for the gate oxide, e.g. , ± r =16and
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This note was uploaded on 11/10/2010 for the course EECE 480 taught by Professor David during the Fall '09 term at UBC.

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exam_final_08 - Department of Electrical and Computer...

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