05_Nonpipelined

05_Nonpipelined - Datapath & Control Readings: 4.1-4.4...

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Readings: 4.1-4.4 Computer Processor Control Datapath Memory Devices Input Output 69 Datapath: System for performing operations on data, plus memory access. Control: Control the datapath in response to instructions. Simple CPU Develop complete CPU for subset of instruction set Memory: lw, sw Branch: beq Arithmetic: addi 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Arithmetic: add, sub Jump: j 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP RS RT RD SHAMT FUNCT OP RS RT 16 bit Address/Immediate 70 Most other instructions similar 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP 26 bit Address
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Execution Cycle Obtain instruction from program storage Determine required actions and instruction size Instruction Fetch Instruction Locate and obtain operand data Compute result value or status Decode Operand Fetch Execute Resul 71 Deposit results in storage for later use Determine successor instruction Result Store Next Instruction Overall Dataflow PC fetches instructions Instructions select operand registers, ALU immediate values ALU computes values Processor Overview Load/Store addresses computed in ALU Result goes to register file or Data memory Instruction Register 72 C Data Memory Memory File
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Convert instructions to Register Transfer Level (RTL) specification RegA = RegB + RegC; RTL specifies required interconnection of units, control Example: Fib(0) = 0; Fib (1) = 1; Fib(I) = Fib (i-1) + Fib (i-2); Compute Fib(N) InitCycle: N = input; Index = 1; Fib(Index) = 1; Fib(index-1) = 0; ComputeCycle: 73 Index Fib(i) Fib(i-1) N Instruction Fetch PC Address Instruction Memory 74
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Add/Subtract RTL Add instruction: add rd, rs, rt Subtract instruction: sub rd, rs, rt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 75 OP RS RT RD SHAMT FUNCT Datapath for Reg/Reg Ops Instruction Fetch Unit Instructions[31:0] [25:21] [20:16] [15:11] Rs Rt Rd ALUcntrl Aw Aa Ab Da Dw Db Register 76 WrEn File RegWr
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Add Immediate RTL Add immediate instruction:
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This note was uploaded on 11/11/2010 for the course ECE 125 taught by Professor Chang during the Spring '10 term at Eastern.

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05_Nonpipelined - Datapath & Control Readings: 4.1-4.4...

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