06_Pipelining

06_Pipelining - Pipelining Readings: 4.5-4.8 Example: Doing...

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Pipelining Readings: 4.5-4.8 Example: Doing the laundry A B C D Ann, Brian, Cathy, & Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes 104 Dryer takes 40 minutes “Folder” takes 20 minutes Sequential Laundry 30 40 20 30 40 20 30 40 20 30 40 20 6 PM 789 10 11 Midnight Time A B C 40 20 30 40 20 30 40 20 30 T a s k O r d 105 Sequential laundry takes 6 hours for 4 loads If they learned pipelining, how long would laundry take? D e r
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Pipelined Laundry: Start work ASAP 6 PM 789 10 11 Midnight Time A B T a s k O r 30 40 40 40 40 20 106 Pipelined laundry takes 3.5 hours for 4 loads C D d e r Pipelining Lessons Pipelining doesn’t help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage 6 PM Time Multiple tasks operating simultaneously using different resources Potential speedup = Number pipe stages Unbalanced lengths of pipe stages reduces speedup A B T a s k O r 30 40 40 40 40 20 107 Time to “ fill ” pipeline and time to drain ” it reduces speedup Stall for Dependences C D d e r
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Pipelined Execution IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB Time IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB Program Flow 108 Now we just have to make it work Single Cycle vs. Pipeline Clk Single Cycle Implementation: Load Store Waste Cycle 1 Cycle 2 Clk Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Load Ifetch Reg Exec Mem Wr Pipeline Implementation: Ifetch Reg Exec Mem Wr Store 109 Ifetch Reg Exec Mem Wr R-type
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Why Pipeline? Suppose we execute 100 instructions Single Cycle Machine 45 ns/cycle x 1 CPI x 100 inst = ns 45 ns/cycle x 1 CPI x 100 inst = ____ ns Ideal pipelined machine 10 ns/cycle x (1 CPI x 100 inst + 4 cycle drain) = ____ ns 110 CPI for Pipelined Processors Ideal pipelined machine 10 ns/cycle x ( 1 CPI x 100 inst + 4 cycle drain) = ____ ns CPI in pipelined processor is “issue rate”. Ignore fill/drain, ignore latency. Example: A processor wastes 2 cycles after every branch, and 1 after every load, during which it cannot issue a new instruction. If a program has 10% branches and 30% loads, what is the CPI on this program? 111
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Divide datapath into multiple pipeline stages Pipelined Datapath IF RF EX MEM WB Register PC Data Memory Instr. Memory Register File Register File Instruction Fetch Register Fetch Execute Data Memory Writeback 112 Pipelined Control The Main Control generates the control signals during Reg/Dec Control signals for Exec (ALUOp, ALUSrcA, …) are used 1 cycle later Control signals for Mem (MemWE, IorD, …) are used 2 cycles later Control signals for Wr (Mem2Reg, RegWE, …) are used 3 cycles later IF/ID ID/Ex Ex/Mem Mem/W Reg/Dec Exec Mem ALUSrcA ALUOp ALUSrcB Main Ct ALUSrcA ALUOp ALUSrcB Wr 113 r Register
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This note was uploaded on 11/11/2010 for the course ECE 125 taught by Professor Chang during the Spring '10 term at Eastern.

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06_Pipelining - Pipelining Readings: 4.5-4.8 Example: Doing...

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