07_Caches

07_Caches - Memory Hierarchy: Caches, Virtual Memory...

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Unformatted text preview: Memory Hierarchy: Caches, Virtual Memory Readings: 5.1-5.3, 5.5 Big memories are slow Processo Computer Memory Devices Fast memories are small Processor Control Datapath Memory Devices Input Output 136 Need to get fast, big memories Random Access Memory Dynamic Random Access Memory (DRAM) High density, low power, cheap, but slow Dynamic since data must be “refreshed” regularly Random Access since arbitrary memory locations can be read Static Random Access Memory Low density, high power, expensive Static since data held as long as power is on Fast access time, often 2 to 10 times faster than DRAM Technology Access Time Cost/Capacity SRAM 1-7 cycles 1000x 137 DRAM 100 cycles 50x Disk 10,000,000 cycles 1x The Problem The Von Neumann Bottleneck Logic gets faster Memory capacity gets larger Memory speed is not keeping up with logic Cost vs. Performance Fast memory is expensive Slow memory can significantly affect performance Design Philosophy Use a hybrid approach that uses aspects of both 138 Keep frequently used things in a small amount of fast/expensive memory “Cache” Place everything else in slower/inexpensive memory (even disk) Make the common case fast Locality Programs access a relatively small portion of the address space at a time char *index = string; while (*index != 0) { /* C strings end in 0 */ if (*index >= ‘a’ && *index <= ‘z’) Types of Locality Temporal Locality – If an item has been accessed recently, it will tend to be *index = *index +(‘A’ - ‘a’); index++; } 139 accessed again soon Spatial Locality – If an item has been accessed recently, nearby items will tend to be accessed soon Locality guides caching The Solution By taking advantage of the principle of locality: Provide as much memory as is available in the cheapest technology. Provide access at the speed offered by the fastest technology. Control Datapath Secondary Storage (Disk) Processor Register Main Memory (DRAM) Second Level Cache (SRAM On-Chi Cache 140 s (SRAM) p Name Register Cache Main Memory Disk Memory Speed 1 cycle 1-7 cycles 100 cycles 10,000,000 cycles Capacity 1x (norm.) 64-4Kx 4Mx 1Gx Cache Terminology Block – Minimum unit of information transfer between levels of the hierarchy Block addressing varies by technology at each level Blocks are moved one level at a time Upper vs. lower level – “upper” is closer to CPU, “lower” is futher away Hit – Data appears in a block in that level Hit rate – percent of accesses hitting in that level Hit time – Time to access this level Hit time = Access time + Time to determine hit/miss Miss – Data does not appear in that level and must be fetched from lower level Miss rate – percent of misses at that level = (1 – hit rate) Miss penalty – Overhead in getting data from a lower level 141 Miss penalty = Lower level access time + Replacement time + Time to deliver to processor Miss penalty is usually MUCH larger than the hit time Cache Access Time Average access time Access time = (hit time) + (miss penalty)x(miss rate)...
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This note was uploaded on 11/11/2010 for the course ECE 125 taught by Professor Chang during the Spring '10 term at Eastern.

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07_Caches - Memory Hierarchy: Caches, Virtual Memory...

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