# 08_AdvArch - Dynamic Branch Prediction Readings: 4.8...

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Unformatted text preview: Dynamic Branch Prediction Readings: 4.8 Branches introduce control hazards Determine the right next instruction in time for instruction fetch Previous solutions: Stall Statically predict not taken Branch Delay slot Better: 178 Branch-prediction buffers (caches) Problems With Static Branch Predictors Are all branches created equal? 179 Branch Prediction Buffer Direct-mapped cache w/1-bit history Predict taken/not taken by previous execution If incorrect prediction, annul instructions incorrectly started Tags? Valid bits? 180 Thought Experiment Consider the following code segment: while (1) { <code 1> for(int i=0; i<9; i++) { addi C, \$0, 9 # Const. 9 WHILE_TOP: <code 1> add i, \$0, \$0 # Init. i j FOR_TEST FOR TOP <code 2> } <code 3> } 1-bit prediction accuracy? FOR_TOP: <code 2> addi i, i, 1 # i++ FOR_TEST: slt \$t0, i, C # i < 9? bneq \$t0,\$0,FOR_TOP <code 3> j WHILE_TOP # Endwhile 181 2-bit Predictor 182 2-bit Predictor (cont.) while (1) { if (normal_condition) { <code1> } 2 Branch Predictor for(int i=0; i<9; i++) { if (exception) { return (FALSE); } <code 2> } if (random 50/50 chance) { # of predictors 183 <code 3> } } Instruction-Level Parallelism & Advanced Architectures Readings: 4.10 Key to pipelining was dealing with hazards Advanced processors require significant hazard avoidance/flexibility ILP = Instruction-Level Parallelism 184 Why ILP Advanced processors optimize two factors: Reduce clock period by heavy pipelining Greater pipelining means more hazards, delay slots Reduce CPI What if we want a CPI < 1.0?...
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## This note was uploaded on 11/11/2010 for the course ECE 125 taught by Professor Chang during the Spring '10 term at Eastern.

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08_AdvArch - Dynamic Branch Prediction Readings: 4.8...

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