EE-271_Rev2

EE-271_Rev2 - Engineer-to-Engineer Note EE-271 Technical...

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Engineer-to-Engineer Note EE-271 Technical notes on using Analog Devices DSPs, processors and development tools Visit our Web resources http://www.analog.com/ee-notes and http://www.analog.com/processors or e-mail processor.support@analog.com or processor.tools.support@analog.com for technical support. Using Cache Memory on Blackfin® Processors Contributed by Kunal Singh & Andreas Pellkofer Rev 2 – May 13, 2009 Copyright 2005-2009, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Engineer-to-Engineer Notes. Introduction This application note discusses cache memory management for Analog Devices Blackfin® processor family. The document introduces popular cache schemes and then discusses the Blackfin instruction cache and the data cache in detail. The described features are available on all Blackfin processors. Example code is provided with this application note to demonstrate cache memory management. It applies to all derivatives of the Blackfin processor family. This document assumes that the reader is familiar with basic cache terminology. Figure 1. ADSP-BF533 block diagram
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Using Cache Memory on Blackfin® Processors (EE-271) Page 2 of 32 Contents Introduction ......................................................................... 1 Contents ................................................................................... 2 Cache Memory Concepts .................................................... 3 Memory Configuration ................................................. 3 Cache Terminology ........................................................ 3 Block Placement ............................................................. 4 Block Replacement ........................................................ 4 Block Identification ................................................. 5 Write Strategies ........................................................... 6 Blackfin Cache Model ....................................................... 6 Blackfin Instruction Cache Configuration ..8 Blackfin Data Cache Configuration ................ 11 Memory Protection and Cache Unit ................... 15 Cacheability Protection Lookaside Buffers (CPLBs) .............................................................................. 15 Memory Pages and Page Attributes ................... 17 CPLB Status Registers ............................................. 18 CPLB-Related Sequencer Exceptions ................ 20 Page Descriptor Table ............................................. 20
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This note was uploaded on 11/11/2010 for the course ECE 125 taught by Professor Chang during the Spring '10 term at Eastern.

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EE-271_Rev2 - Engineer-to-Engineer Note EE-271 Technical...

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