Unformatted text preview: based upon the MIPS instruction set. Note that the labs GROW SIGNIFICANTLY in the amount of time it takes to complete them. The average time to complete the labs is expected to be: Lab 1: Register File 12 hours Lab 2: ALU 11 hours Lab 3: Single-cycle CPU 25 hours Lab 4: Pipelined CPU 34 hours Exams: There will be one midterm (11/16) and one final exam (8:30-10:20 Wed 12/15). Grade: The grade will be determined by the following approximate weights: homeworks (15%), design project (40%), midterm (20%), final exam (25%). Outline: The class will have the following approximate schedule. Material may be added or dropped based on class timing and progress. * Introduction to processor architecture. * Assembly language programming. * Computer Arithmetic. * Performance measures. * Processor Datapaths & Control. * Pipelining. * Memory hierarchy, caches, virtual memory. * Advanced topics in computer architecture. Website: http://www.ee.washington.edu/class/471/hauck/...
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- Spring '10
- Microprocessor, Central processing unit, Prof. Scott Hauck, Roman Lysecky Verilog