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verilogRefCard - 3 PARALLEL STATEMENTS assign(strength1...

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Verilog HDL QUICK REFERENCE CARD Revision 2.1 () Grouping [ ] Optional {} Repeated | Alternative bold As is CAPS User Identifier 1. M ODULE module MODID[ ( {PORTID , } ) ] ; [ input | output | inout [range] {PORTID , } ; ] [{declaration}] [{parallel_statement}] [specify_block] endmodule range ::= [ constexpr : constexpr ] 2. D ECLARATIONS parameter {PARID = constexpr , } ; wire | wand | wor [range] {WIRID , } ; reg [range] {REGID [range] , } ; integer {INTID [range] , } ; time {TIMID [range] , } ; real {REALID , } ; realtime {REALTIMID , } ; event {EVTID , } ; task TASKID; [{ input | output | inout [range] {ARGID , } ; }] [{declaration}] begin [{sequential_statement}] end endtask function [range] FCTID; { input [range] {ARGID , } ; } [{declaration}] begin [{sequential_statement}] end endfunction 3. P ARALLEL S TATEMENTS assign [ ( strength 1, strength 0) ] WIRID = expr ; initial sequential_statement always sequential_statement MODID [ #( {expr , } ) ] INSTID ( [{expr , } | { . PORTID ( expr ), }] ); GATEID [ ( strength 1, strength 0) ] [ # delay] [INSTID] ( {expr , } ); defparam {HIERID = constexpr , } ; strength ::= supply | strong | pull | weak | highz delay ::= number | PARID | ( expr [ , expr [ , expr]] ) 4. G ATE P RIMITIVES and ( out , in 1 , ..., in N ); nand ( out , in 1 , ..., in N ); or ( out , in 1 , ..., in N ); nor ( out , in 1 , ... , in N ); xor ( out , in 1 , ... , in N ); xnor ( out , in 1 , ... , in N ); buf ( out 1 , ... , out N , in ); not ( out 1 , ... , out N , in ); bufif0 ( out , in , ctl ); bufif1 ( out , in , ctl ); notif0 ( out , in , ctl ); notif1 ( out , in , ctl ); pullup ( out ); pulldown ( out ); [ r ] pmos ( out , in , ctl ); [ r ] nmos ( out , in , ctl ); [ r ] cmos ( out , in , nctl , pctl ); [ r ] tran ( inout , inout ); [ r ] tranif1 ( inout , inout , ctl ); [ r ] tranif0 ( inout , inout , ctl ); 5. S EQUENTIAL S TATEMENTS ; begin [ : BLKID [{declaration}]] [{sequential_statement}] end if ( expr ) sequential_statement [ else sequential_statement] case | casex | casez ( expr ) [{{expr , } : sequential_statement}] [ default: sequential_statement]
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This note was uploaded on 11/11/2010 for the course ECE 125 taught by Professor Chang during the Spring '10 term at Eastern.

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verilogRefCard - 3 PARALLEL STATEMENTS assign(strength1...

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