VerilogTutorial

VerilogTutorial - 271/471 Verilog Tutorial Prof. Scott...

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271/471 Verilog Tutorial Prof. Scott Hauck, last revised 10/9/09 Introduction The following tutorial is intended to get you going quickly in gate-level circuit design in Verilog. It isn’t a comprehensive guide to Verilog, but should contain everything you need to design circuits for your class. If you have questions, or want to learn more about the language, I’d recommend Samir Palnitkar’s Verilog HDL: A Guide to Digital Design and Synthesis . Modules The basic building block of Verilog is a module. This is similar to a function or procedure in C/C++/Java in that it performs a computation on the inputs to generate an output. However, a Verilog module really is a collection of logic gates, and each time you call a module you are creating that set of gates. An example of a simple module: AND_OR andOut orOut A B TheAndGate TheOrGate // Compute the logical AND and OR of inputs A and B. module AND_OR(andOut, orOut, A, B); output andOut, orOut; input A, B; and TheAndGate (andOut, A, B); or TheOrGate (orOut, A, B); endmodule We can analyze this line by line: // Compute the logical AND and OR of inputs A and B. The first line is a comment, designated by the //. Everything on a line after a // is ignored. Comments can appear on separate lines, or at the end of lines of code. module AND_OR(andOut, orOut, A, B);
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output andOut, orOut; input A, B; The top of a module gives the name of the module (AND_OR in this case), and the list of signals connected to that module. The subsequent lines indicate that the first two binary values (andOut and orOut) are generated by this module, and are output from it, while the next two (A, B) are inputs to the module. and TheAndGate (andOut, A, B); or TheOrGate (orOut, A, B); This creates two gates: An AND gate, called “TheAndGate”, with output andOut, and inputs A and B; An OR gate, called “TheOrGate”, with output orOut, and inputs A and B. The format for creating or “instantiating” these gates is explained below. endmodule All modules must end with an endmodule statement. Basic Gates Simple modules can be built from several different types of gates: buf <name> (OUT1, IN1); // Sets output equal to input not <name> (OUT1, IN1); // Sets output to opposite of input The <name> can be whatever you want, but start with a letter, and consist of letters, numbers, and the underscore “_”. Avoid keywords from Verilog (i.e. “module”, “output”, etc.). There are multi-input gates as well, which can each take two or more inputs: and <name> (OUT, IN1, IN2); // Sets output to AND of inputs or <name> (OUT, IN1, IN2); // Sets output to OR of inputs nand <name> (OUT, IN1, IN2); // Sets to NAND of inputs nor <name> (OUT, IN1, IN2); // Sets output to NOR of inputs xor <name> (OUT, IN1, IN2); // Sets output to XOR of inputs xnor <name> (OUT, IN1, IN2); // Sets to XNOR of inputs If you want to have more than two inputs to a multi-input gate, simply add more. For example, this is a five-input and gate:
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VerilogTutorial - 271/471 Verilog Tutorial Prof. Scott...

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