Exercise_Midterm2

Exercise_Midterm2 - Propagation delay of 100ps...

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MORE EXERCISES FOR MIDTERM # 2 1. (Flip-Flops) a. What is the difference between a latch and a flip-flop? b. Implement a JK flip-flop with a T flip-flop and a minimal AND- OR-NOT network. Let us assume that the complements of J, K and Q signals are available. Draw the logic diagram to show your design. 2. (Design Specification) Write the state table of the sequential circuit as the following figure. 3. (Sequential Circuit Design) A state machine is described by the following state equations: a. Write the state table b. Design the system with two JK flip-flops and a minimal AND-OR-NOT network. 4. (Timing) In the following circuit Each flip flop has: Setup time of 60ps Hold time of 20ps Clock-to-Q maximum delay of 70ps Clock-to-Q minimum delay of 50ps Each XOR gate has:
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Unformatted text preview: Propagation delay of 100ps Contamination delay of 55ps a. If there is no clock skew, what is the maximum operating frequency of this circuit? b. How much clock skew can the circuit tolerate before it might experience a hold time violation? c. Redesign the circuit so that it can be operated at 3GHz frequency. How much clock skew can your circuit tolerate before it might experience a hold time violation? 5. (Decoders and Multiplexers) Given a three-input Boolean function f(a; b; c) = ∑m(0, 1, 2, 3, 7). a. Implement the function using a minimal network of 2:4 decoders and OR gates. b. Implement the function using a minimal network of 4:1 multiplexers. c. Implement the function using a minimal network of 2:1 multiplexers....
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This note was uploaded on 11/11/2010 for the course CSE 140 taught by Professor Rosing during the Fall '06 term at UCSD.

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Exercise_Midterm2 - Propagation delay of 100ps...

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