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Unformatted text preview: CSE 260 – Digital Computers: Organization and Logical Design Homework 3b Solutions
Jon Turner Due 2/21/2008 1. (10 points) Consider the SR latch shown on page 3-18 of the lecture notes. Assume the NOR gates each have a delay of exactly 1 ns and suppose that at time 0, the latch is cleared (Q=0) and the S and R inputs are both low. Then at time 10 ns, S and R both go high and at time 20 ns, they both go low. Draw a timing diagram showing how the outputs change in response to this. -1- 2. (10 points) The diagram shown below shows a negative edge-triggered D flip flop and an SR master-slave flip flop with labels added to some intermediate signals. Complete the timing diagram shown below, assuming that every gate has a delay equal to half of one time unit. Explain how the behavior of the SR flip flop is similar to the behavior of the D flip flop and how it is different. D A Q1 C S R C
0 C D A Q1 S R B Q2 4 8 12 16 20 24 28 B Q2 -2- ...
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- Spring '10
- Logic gate, Input/output, Latch, Jon Turner