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Unformatted text preview: CSE 260 – Digital Computers: Organization and Logical Design Homework 3b Solutions
Jon Turner 1. (10 points) Consider the SR latch shown on page 3-18 of the lecture notes. Assume the NOR gates each have a delay of exactly 1 ns and suppose that at time 0, the latch is cleared (Q=0) and the S and R inputs are both low. Then at time 10 ns, S and R both go high and at time 20 ns, they both go low. Draw a timing diagram showing how the outputs change in response to this. S R Q Q’ -1- 2. (10 points) The diagram shown below shows a negative edge-triggered D flip flop and an SR master-slave flip flop with labels added to some intermediate signals. Complete the timing diagram shown below, assuming that every gate has a delay equal to half of one time unit. Explain how the behavior of the SR flip flop is similar to the behavior of the D flip flop and how it is different. D A Q1 C S R C
0 C D A Q1 S R B Q2 4 8 12 16 20 24 28 B Q2 The behavior of the two flip flops is similar in the sense that the outputs of both flip flops change when the clock goes from high to low. They are different in that the SR flip flop responds to changes that occur while the clock is high, while the D flip flop responds only to the value of the input at the time the clock drops. For example, when the clock drops at time 6, we see that the output of the SR flip flop changes, even though both of the inputs are low when the clock drops. This happens because during the period the clock is high, the S input went high, causing the master latch to become set. This new value then appears at the output when the clock drops. On the other hand, we see that even though the D input is high at time 20 (causing signal A to also be high), the value of the flip flop output is not affected by this. -2- ...
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This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.
- Spring '10