hw4a - z when a = 000 else b+c when a = 011 else c when...

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- 1 - 1. (10 points) Rewrite the following VHDL module using only ordinary signal assignments (no conditional assignments). entity foo is port( a,b,c,d: in std_logic; x: out std_logic; y: out std_logic_vector (1 downto 0); end entity foo; architecture arch of foo begin x <= b and c when a = ‘0’ else not c when a>b else a or d; y <= (a & d) when a = ‘1’ else (b & (not c)) when (b=‘0’ and c=‘1’) else ‘1’ & c; end arch; 2. (10 points) Draw a circuit corresponding to the following VHDL module. entity foo is port( a: in std_logic_vector(2 to 0); b,c,d: in std_logic_vector(3 downto 0); x,y: out std_logic_vector(3 downto 0)); end entity foo; architecture arch of foo signal z: std_logic_vector(3 downto 0); begin z <= b xor c; with a select x <= z when “000”, c when “001” | “100”, d when “110” | “111” | “101”, b+c when “011”, c+d when others; y <= c+d when a = “010” else d when a >= “101” and a <= “111” else
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Unformatted text preview: z when a = 000 else b+c when a = 011 else c when others; end arch; CSE 260 Digital Computers: Organization and Logical Design Homework 4a Jon Turner - 2 - 3. (10 points) Rewrite the VHDL module in the previous problem using a process block and an if-then-else statement. 4. (10 points) Draw a circuit corresponding to the following VHDL module. You may use labeled circuit blocks for combinational subcircuits that implement addition or comparison operations. entity foo is port( a,b,c,d: in std_logic_vector(3 to 0); w,x,y: out std_logic_vector(3 downto 0)); end entity foo; architecture arch of foo signal z: std_logic_vector(3 downto 0); begin process (a,b,c,d,z) begin x &lt;= a; y &lt;= z; if b = c then y &lt;= b + d; z &lt;= a; elsif a &gt; b then x &lt;= c xor d; z &lt;= not b; else z &lt;= a and c; end if; end process; w &lt;= b or z; end arch; 5. (10 points) Rewrite the VHDL module in the previous problem using conditional signal assignments only....
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This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.

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hw4a - z when a = 000 else b+c when a = 011 else c when...

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