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Unformatted text preview: z when a = 000 else b+c when a = 011 else c when others; end arch; CSE 260 Digital Computers: Organization and Logical Design Homework 4a Jon Turner - 2 - 3. (10 points) Rewrite the VHDL module in the previous problem using a process block and an if-then-else statement. 4. (10 points) Draw a circuit corresponding to the following VHDL module. You may use labeled circuit blocks for combinational subcircuits that implement addition or comparison operations. entity foo is port( a,b,c,d: in std_logic_vector(3 to 0); w,x,y: out std_logic_vector(3 downto 0)); end entity foo; architecture arch of foo signal z: std_logic_vector(3 downto 0); begin process (a,b,c,d,z) begin x <= a; y <= z; if b = c then y <= b + d; z <= a; elsif a > b then x <= c xor d; z <= not b; else z <= a and c; end if; end process; w <= b or z; end arch; 5. (10 points) Rewrite the VHDL module in the previous problem using conditional signal assignments only....
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This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.
- Spring '10