hw4aSol - 1 1(10 points Rewrite the following VHDL module...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: - 1 - 1. (10 points) Rewrite the following VHDL module using only ordinary signal assignments (no conditional assignments). entity foo is port( a,b,c,d: in std_logic; x: out std_logic; y: out std_logic_vector (1 downto 0); end entity foo; architecture arch of foo begin x <= b and c when a = ‘0’ else not c when a>b else a or d; y <= (a & d) when a = ‘1’ else (b & (not c)) when (b=‘0’ and c=‘1’) else ‘1’ & c; end arch; The revised version of the architecture appears below. These assignments were derived by first simplifying the expressions given above. entity foo is port( a,b,c,d: in std_logic; x: out std_logic; y: out std_logic_vector (1 downto 0); end entity foo; architecture arch of foo begin x <= ((not a) and b and c) or (a and (not b) and (not c)) or (a and b); y(1) <= a or b or (not c); y(0) <= (a and d) or ((not a) and b and c); end arch; CSE 260 – Digital Computers: Organization and Logical Design Homework 4a Solutions Jon Turner - 2 - 2. (10 points) Draw a circuit corresponding to the following VHDL module. (10 points) Draw a circuit corresponding to the following VHDL module....
View Full Document

{[ snackBarMessage ]}

Page1 / 5

hw4aSol - 1 1(10 points Rewrite the following VHDL module...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online