# hw4b - CSE 260 Digital Computers Organization and Logical...

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Unformatted text preview: CSE 260 Digital Computers: Organization and Logical Design Homework 4b Jon Turner Due 1/29/2008 1. (10 points) Write a VHDL module using a case statement that is implemented by the following circuit. a x b c d y p 3 0 12 3 4 56 7 3 8 decoder 2. (10 points) Show how to replace the for-loop in the VHDL module shown below with a pair of signal assignments to vectors. entity foo is port( a,b: in std_logic_vector(3 downto 0); x: out std_logic_vector(3 downto 0); end entity foo; architecture arch of foo signal z: std_logic_vector(4 downto 0); begin process (a,b,z) begin z(0) <= `0'; for i in 0 downto 3 loop x(i) <= (a(i) and b(i)) xor z(i); z(i+1) <= a(i) or z(i); end loop end process; end arch; -1- 3. (10 points) Draw a circuit corresponding to the following VHDL module. entity comparator is port( a,b: in std_logic_vector(3 to 0); aGreaterThanB, bGreaterThanA: out std_logic); end entity comparator; architecture arch of comparator signal gt, lt: std_logic_vector(4 downto 0); begin process (a,b,gt,lt) begin gt(4) <= `0'; lt(4) <= `0'; for i in 3 downto 0 loop if gt(i+1) = `1' or (lt(i+1) = `0' and a(i) > b(i)) then gt(i) <= `1'; else gt(i) <= `0'; end if; if lt(i+1) = `1' or (gt(i+1) = `0' and a(i) < b(i)) then lt(i) <= `1'; else lt(i) <= `0'; end if; end loop aGreaterThanB <= gt(0); bGreaterThanA <= lt(0); end process; end arch; 4. (10 points) Write a VHDL specification of the circuit in the diagram shown below. a 1 0 D >C Q z x b 1 0 1 0 D >C Q y c d s clk -2- ...
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hw4b - CSE 260 Digital Computers Organization and Logical...

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