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hw4bSol - CSE 260 Digital Computers Organization and...

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- 1 - 1. (10 points) Write a VHDL module using a case statement that is implemented by the following circuit. entity foo is port( a,b,c,d: in std_logic; p: in std_logic_vector(2 downto 0); x,y: out std_logic); end entity; architecture bar of foo is signal xx, yy: std_logic; begin process(a,b,c,d,p) begin xx <= ‘0’; yy <= ‘0’; case p is when “000” => xx <= a and b; when “010” => xx <= a or c; when “011” => yy <= d; when “100” => yy <= c xor d; when “101” => xx <= b; when “110” => yy <= b and d; when “111” => yy <= c; when others => end case; x <= xx or a; y <= yy or c or d; end process; end bar; CSE 260 – Digital Computers: Organization and Logical Design Homework 4b Solutions Jon Turner a d y x b c p 3 3 Ö 8 decoder 0 2 4 6 1 3 5 7
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- 2 - 2. (10 points) Show how to replace the for-loop in the VHDL module shown below with a pair of signal assignments to vectors. entity foo is port( a,b: in std_logic_vector(3 downto 0); x: out std_logic_vector(3 downto 0); end entity foo; architecture arch of foo signal z: std_logic_vector(4 downto 0); begin process (a,b,z) begin z(0) <= ‘0’;
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