Hw4c - z out std_logic_vector(7 downto 0 end foo architecture arch of foo is signal x std_logic_vector(7 downto 0 begin process(clk,a,b,c,x

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- 1 - 1. (10 points) Write a VHDL module that has a single 4 bit input x and returns an 3 bit value equal to the square root of x , rounded up to the nearest integer. Implement your circuit using a table of constants. You will need the following function declaration that converts a signal of type std_logic_vector to integer , since the index used in an array must be of type integer . function int(d: std_logic_vector) return integer is -- Convert logic vector to integer. Handy for array indexing. begin return conv_integer(unsigned(d)); end function int; 2. (20 points) Draw a circuit diagram that implements the VHDL module shown below. entity foo is port ( clk: in std_logic; a,b,c: in std_logic_vector(7 downto 0);
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Unformatted text preview: z: out std_logic_vector(7 downto 0)); end foo; architecture arch of foo is signal x: std_logic_vector(7 downto 0); begin process (clk,a,b,c,x) function mid(u,v,w: std_logic_vector(7 downto 0)) return std_logic_vector is begin if u > v then if v > w then return v; else return w; end if; else if v < w then return v; else return w; end if; end if; end function mid; begin if rising_edge(clk) then if a>c then x <= mid(a,b,c); else x <= mid(a,b,x); end if; end if; if a>b then z <= mid(a,b,c); elsif b>c then z <= mid(a,b,x); else z <= mid(a,c,x); end if; end process; end arch; CSE 260 – Digital Computers: Organization and Logical Design Homework 4c Jon Turner Due 2/7/2008...
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This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.

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