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hw4cSol - CSE 260 Digital Computers Organization and...

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- 1 - 1. (10 points) Write a VHDL module that has a single 4 bit input x and returns a 3 bit value equal to the square root of x , rounded up to the nearest integer. Implement your circuit using a table of constants. You will need the following function declaration that converts a signal of type std_logic_vector to integer , since the index used in an array must be of type integer . function int(d: std_logic_vector) return integer is -- Convert logic vector to integer. Handy for array indexing. begin return conv_integer(unsigned(d)); end function int; entity getSqrt is port ( x: in std_logic_vector(3 downto 0); sqrt: out std_logic_vector(2 downto 0)); end getSqrt; The complete VHDL module is shown below. architecture arch of getSqrt is type table is array(0 to 15) of std_logic_vector(2 downto 0); signal sqrTbl: table := ( "000", "001", "010", "010", "010", "011", "011", "011", "011", "011", "100", "100", "100", "100", "100", "100" ); function int(d: std_logic_vector) return integer is -- Convert logic vector to integer. Handy for array indexing. begin return conv_integer(unsigned(d)); end function int;
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