This preview shows page 1. Sign up to view the full content.
Unformatted text preview: CSE 260 – Digital Computers: Organization and Logical Design Homework 6c
Jon Turner Due 2/19/2008 1. (15 points) Write a VHDL module that implements a serial inrange circuit. This is a circuit that determines if an input value x is numerically in between two other input values a and b. All three of the data inputs are input to the circuit one bit at a time with the mostsignificantbit first. The circuit has a single output value called inRange which should be high, if the portion of x that has been seen so far is numerically in between the portion of a and b that has been seen so far. Note that a may be less than, greater than or equal to b. So for example, if the stream of input bits for a is 1001 0101 (with most significant bit first), b is 1000 0101 and x is 1001 0110 then inRange will be 1111 1100. Your circuit should also have a reset input and when reset is high, inRange should be low. The first output bit should appear just after the first rising clock edge after reset drops, with subsequent bits on every successive clock tick. Start by writing down the state transition diagram for your circuit. Then write your VHDL based directly on your state transition diagram. 2. (15 points) Consider the state transition diagram shown below. Design a test sequence that causes the state machine to pass through every state and exercises every transition. You can specify this as a bit string for each of the two inputs A and B. Give a VHDL testbench that implements this test sequence (you need not write the VHDL for the entire sequence, just the first few input values for A and B. 01/0
red 1x/0 01/0 1x/0 00/0 00/1 00/0 10/1 green 01/1 1x/0
blue 11/1 00/1 yellow 01/0 1 ...
View
Full
Document
This note was uploaded on 11/12/2010 for the course KTMT KTMT04 taught by Professor Son during the Spring '10 term at Dallas Colleges.
 Spring '10
 Son

Click to edit the document details