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Unformatted text preview:  1  1. (15 points) Write a VHDL module that implements a serial inrange circuit. This is a circuit that determines if an input value x is numerically in between two other input values a and b . All three of the data inputs are input to the circuit one bit at a time with the most significantbit first. The circuit has a single output value called inRange which should be high, if the portion of x that has been seen so far is numerically in between the portion of a and b that has been seen so far. Note that a may be less than, greater than or equal to b . So for example, if the stream of input bits for a is 1001 0101 (with least significant bit first), b is 1000 0101 and x is 1001 0110 then inRange will be 1111 1100. Your circuit should also have a reset input and when reset is high, inRange should be low. The first output bit should appear just after the first rising clock edge after reset drops, with subsequent bits on every successive clock tick. Start by writing down the state transition diagram for your circuit....
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 Spring '10
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 state transition diagram, inRange

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