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hw7_2 - that gate delays for simple gates can range from.4...

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- 1 - 1. (10 points) Determine if the circuit below is subject to internal hold time violations. If so, show how to modify the circuit to eliminate the hold time violations. If not, explain why not. Assume that the flip flop setup time is 2 ns, the hold time is 1 ns, that gate delays for simple gates can range from .3 ns to 1.5 ns, that gates with 3 or 4 inputs have twice as much delay as simple gates, that the flip flop propagation delay can range from 1 ns to 4 ns and that the clock skew is 1 ns. CSE 260 – Digital Computers: Organization and Logical Design Homework 7 Jon Turner Due 2/26/2008
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- 2 - 2. (10 points) Determine the shortest clock period that can be used without causing any internal setup time violations in the circuit shown below. What maximum clock frequency does this correspond to? Assume that the flip flop setup time is 2 ns, the hold time is 1 ns,
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Unformatted text preview: that gate delays for simple gates can range from .4 ns to 1.5 ns, that gates with 3 or 4 inputs have twice as much delay as simple gates, that the flip flop propagation delay can range from 1 ns to 4 ns and that the clock skew is 1 ns. - 3 - 3. (10 points ) Consider a synchronizer used to synchronize an asynchronous input signal. Let the average time between changes of the input signal be 50 microseconds. Let the flip flop parameters be T = 3 ns and τ = 2 ns. If the clock period for the synchronizer is 10 ns, what is the mean time between synchronizer failures? What is the smallest clock period (to the nearest ns) for which the mean time between failures is 10 years? What is the smallest clock period for which the mean time between failures is 10,000 years?...
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