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hw7Sol - CSE 260 Digital Computers Organization and Logical...

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- 1 - 1. (10 points) Determine if the circuit below is subject to internal hold time violations. If so, show how to modify the circuit to eliminate the hold time violations. If not, explain why not. Assume that the flip flop setup time is 2 ns, the hold time is 1 ns, that gate delays for simple gates can range from .3 ns to 1.5 ns, that gates with 3 or 4 inputs have twice as much delay as simple gates, that the flip flop propagation delay can range from 1 ns to 4 ns and that the clock skew is 1 ns. In this circuit, the shortest path from a flip flop output to a flip flop input contains 3 gate delays and since 1 + 3 × .3 < 1 + 1, we would normally conclude that it is subject to internal hold time violations. However, this shortest path goes from the output of the bottom flip flop back to its input, and so we need not include the clock skew on the right side of the inequality, allowing us to conclude that this is not a hold-time violation. All other feedback paths have at least 4 gate delays and since 1 + 4
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hw7Sol - CSE 260 Digital Computers Organization and Logical...

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