hw9b - Run the synthesizer on the new version of the...

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- 1 - 1. (15 points) In the WashU-1 processor, the memory control signals and the address and data bus signals are defined by synchronous assignments (that is, the assignments fall within the scope of a synchronization condition). Rewrite the VHDL so that these signals are defined by asynchronous assignments (that is, outside the scope of any synchronization condition), but have essentially the same timing behavior as in the original version.
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Unformatted text preview: Run the synthesizer on the new version of the WashU-1 to determine the number of flip flops and the maximum clock frequency. Compare these results to numbers reported for the original version. Discuss the differences you observe. Include a printout of your modified VHDL. CSE 260 – Digital Computers: Organization and Logical Design Homework 9b Jon Turner Due 4/1/2008...
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